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Remove slt_or_branch control signal

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Olof Kindgren
2025-03-01 16:49:20 +01:00
parent 842c2df0ca
commit 129a9294c6
3 changed files with 11 additions and 11 deletions
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13
rtl/serv_state.v
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@@ -40,7 +40,8 @@ module serv_state
input wire i_branch_op,
input wire i_shift_op,
input wire i_sh_right,
input wire i_slt_or_branch,
input wire i_alu_rd_sel1,
input wire i_rd_alu_en,
input wire i_e_op,
input wire i_rd_op,
//MDU
@@ -95,10 +96,14 @@ module serv_state
//Prepare RF for writes when everything is ready to enter stage two
// and the first stage didn't cause a misalign exception
assign o_rf_wreq = !misalign_trap_sync & !o_cnt_en & init_done &
((i_shift_op & (i_sh_done | !i_sh_right)) |
//Left shifts, SLT & Branch ops. First cycle after init
//Right shift. o_sh_done
//Mem ops. i_dbus_ack
//MDU ops. i_mdu_ready
assign o_rf_wreq = (i_shift_op & (i_sh_right ? (i_sh_done & !o_cnt_en & init_done) : stage_two_req)) |
i_dbus_ack | (MDU & i_mdu_ready) |
i_slt_or_branch);
(i_branch_op & stage_two_req & !misalign_trap_sync) |
(i_rd_alu_en & i_alu_rd_sel1 & stage_two_req);
assign o_dbus_cyc = !o_cnt_en & init_done & i_dbus_en & !i_mem_misalign;