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Fix CMOD A7 servant target

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This commit is contained in:
Olof Kindgren 2023-05-17 10:13:02 +02:00
parent d7006634cb
commit 1327774f02
5 changed files with 85 additions and 8 deletions
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4
data/cmod_a7_35t.xdc
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@ -7,8 +7,10 @@ set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { q }];
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
## UART
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { o_uart_tx }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { i_rst }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

7
doc/servant.rst
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@ -52,6 +52,13 @@ FPGA Pin W14 (1V8, pin 5 low speed connector) is used for UART Tx output with 11
fusesoc run --target=chameleon96 servant
CMOD A7 35t
^^^^^^^^^^^
FPGA Pin J18 is used for UART output with 57600 baud rate. btn0 is used for reset.
fusesoc run --target=cmod_a7_35t servant
DE0 Nano
^^^^^^^^

14
servant.core
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@ -77,8 +77,8 @@ filesets:
cmod_a7_35t:
files:
- servant/servix_clock_gen.v : {file_type : verilogSource}
- servant/servix.v : {file_type : verilogSource}
- servant/servant_cmod_a7_clock_gen.v : {file_type : verilogSource}
- servant/servant_cmod_a7.v : {file_type : verilogSource}
- data/cmod_a7_35t.xdc : {file_type : xdc}
cyc1000:
@ -243,12 +243,12 @@ targets:
toplevel: CV_96
cmod_a7_35t:
default_tool: vivado
filesets : [mem_files, soc, cmod_a7_35t]
parameters : [memfile=blinky.hex, memsize, frequency=12]
tools:
vivado: {part : xc7a35tcpg236-1}
toplevel : servix
flow: vivado
flow_options:
part : xc7a35tcpg236-1
parameters : [memfile, memsize]
toplevel : servant_cmod_a7
cyc1000:
default_tool: quartus

33
servant/servant_cmod_a7.v Normal file
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@ -0,0 +1,33 @@
`default_nettype none
module servant_cmod_a7
(
input wire i_clk,
input wire i_rst,
output wire o_uart_tx,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign o_uart_tx = q;
servant_cmod_a7_clock_gen
clock_gen
(.i_clk (i_clk),
.i_rst (i_rst),
.o_clk (wb_clk),
.o_rst (wb_rst));
servant
#(.memfile (memfile),
.memsize (memsize))
servant
(.wb_clk (wb_clk),
.wb_rst (wb_rst),
.q (q));
endmodule
`default_nettype wire

35
servant/servant_cmod_a7_clock_gen.v Normal file
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@ -0,0 +1,35 @@
`default_nettype none
module servant_cmod_a7_clock_gen
(input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
MMCME2_BASE
#(.CLKIN1_PERIOD (83.333), //12MHz
/* Set VCO frequency to 12*64=768 MHz
Allowed values are 2.0 to 64.0. Resulting VCO freq
needs to be 600-1200MHz */
.CLKFBOUT_MULT_F (64.000),
.CLKOUT0_DIVIDE_F (48.000)) // 768/48 = 16 MHz
pll
(.CLKIN1 (i_clk),
.RST (i_rst),
.CLKOUT0 (o_clk),
.LOCKED (locked),
.CLKFBOUT (clkfb),
.CLKFBIN (clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule
`default_nettype wire