github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-01-13 23:25:57 +00:00
Code Issues Releases Wiki Activity

Merge LSB registers into bufreg

Browse Source
This commit is contained in:
Olof Kindgren 2021-01-06 23:33:49 +01:00
parent fe6c9b0f83
commit 17103dd1f5
2 changed files with 20 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
rtl/serv_bufreg.v
View File

@ -20,7 +20,7 @@ module serv_bufreg
wire c, q;
reg c_r;
reg [31:0] data;
reg [31:2] data;
wire clr_lsb = i_cnt0 & i_clr_lsb;
@ -31,13 +31,14 @@ module serv_bufreg
c_r <= c & i_en;
if (i_en)
data <= {i_init ? q : o_q, data[31:1]};
data <= {i_init ? q : o_q, data[31:3]};
if (i_init ? (i_cnt0 | i_cnt1) : i_en)
o_lsb <= {i_init ? q : data[2],o_lsb[1]};
if ((i_cnt0 | i_cnt1) & i_init)
o_lsb <= {q,o_lsb[1]};
end
assign o_q = data[0];
assign o_dbus_adr = {data[31:2], 2'b00};
assign o_q = o_lsb[0];
assign o_dbus_adr = {data, 2'b00};
endmodule

16
rtl/serv_state.v
View File

@ -67,7 +67,7 @@ module serv_state
assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3];
assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0];
assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3];
assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init;
//Take branch for jump or branch instructions (opcode == 1x0xx) if
@ -94,8 +94,18 @@ module serv_state
assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init;
//Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting
assign o_bufreg_en = o_cnt_en | (!stage_two_req & i_shift_op);
/*
bufreg is used during mem. branch and shift operations
mem : bufreg is used for dbus address. Shift in data during phase 1.
Shift out during phase 2 if there was an misalignment exception.
branch : Shift in during phase 1. Shift out during phase 2
shift : Shift in during phase 1. Continue shifting between phases (except
for the first cycle after init). Shift out during phase 2
*/
assign o_bufreg_en = (o_cnt_en & (o_init | o_ctrl_trap | i_branch_op)) | (!stage_two_req & i_shift_op);
assign o_ibus_cyc = ibus_cyc & !i_rst;