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privilege tests fixed for rv32i

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Abd
2022-06-13 19:14:57 +05:00
committed by Olof Kindgren
parent 302224834b
commit 1beb9d33ec
2 changed files with 3 additions and 3 deletions
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4
rtl/serv_state.v
View File

@@ -1,7 +1,7 @@
module serv_state
#(parameter RESET_STRATEGY = "MINI",
parameter [0:0] WITH_CSR = 1,
parameter [0:0] COMPRESSED =0,
parameter [0:0] ALIGN =0,
parameter [0:0] MDU = 0)
(
input wire i_clk,
@@ -187,7 +187,7 @@ module serv_state
//trap_pending is only guaranteed to have correct value during the
// last cycle of the init stage
wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !COMPRESSED) |
wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) |
(i_dbus_en & i_mem_misalign));
always @(posedge i_clk) begin

2
rtl/serv_top.v
View File

@@ -224,7 +224,7 @@ module serv_top
#(.RESET_STRATEGY (RESET_STRATEGY),
.WITH_CSR (WITH_CSR),
.MDU(MDU),
.COMPRESSED(COMPRESSED))
.ALIGN(ALIGN))
state
(
.i_clk (clk),