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Small optimization of instruction fetching logic

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Olof Kindgren
2020-08-26 16:44:58 +02:00
parent 3aa1a2c6e5
commit 25e86fdd3c
1 changed files with 4 additions and 9 deletions
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13
rtl/serv_ctrl.v
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@@ -72,16 +72,11 @@ module serv_ctrl
pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
if (i_pc_en) begin
en_pc_r <= 1'b1;
o_ibus_adr <= {new_pc, o_ibus_adr[31:1]};
end else if (o_ibus_cyc & i_ibus_ack)
en_pc_r <= 1'b0;
if (o_ibus_cyc & i_ibus_ack | i_pc_en | i_rst)
en_pc_r <= i_pc_en | i_rst;
if (i_rst) begin
en_pc_r <= 1'b1;
o_ibus_adr <= RESET_PC;
if (i_pc_en | i_rst) begin
o_ibus_adr <= i_rst ? RESET_PC : {new_pc, o_ibus_adr[31:1]};
end
end
endmodule