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Add compatibility with Xilinx ISE

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This commit is contained in:
Gwenhael Goavec-Merou 2020-05-06 20:07:29 +02:00 committed by Olof Kindgren
parent c0fc72b353
commit 2a76adc8db
3 changed files with 6 additions and 5 deletions
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5
rtl/serv_rf_ram_if.v
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@ -2,7 +2,8 @@
module serv_rf_ram_if module serv_rf_ram_if
#(parameter width=8, #(parameter width=8,
parameter csr_regs=4, parameter csr_regs=4,
parameter depth=32*(32+csr_regs)/width) parameter depth=32*(32+csr_regs)/width,
parameter l2w = $clog2(width))
( (
//SERV side //SERV side
input wire i_clk, input wire i_clk,
@ -27,8 +28,6 @@ module serv_rf_ram_if
output wire [$clog2(depth)-1:0] o_raddr, output wire [$clog2(depth)-1:0] o_raddr,
input wire [width-1:0] i_rdata); input wire [width-1:0] i_rdata);
localparam l2w = $clog2(width);
reg rgnt; reg rgnt;
assign o_ready = rgnt | i_wreq; assign o_ready = rgnt | i_wreq;

4
rtl/serv_rf_top.v
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@ -3,7 +3,8 @@
module serv_rf_top module serv_rf_top
#(parameter RESET_PC = 32'd0, #(parameter RESET_PC = 32'd0,
parameter WITH_CSR = 1, parameter WITH_CSR = 1,
parameter RF_WIDTH = 2) parameter RF_WIDTH = 2,
parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
( (
input wire clk, input wire clk,
input wire i_rst, input wire i_rst,
@ -44,7 +45,6 @@ module serv_rf_top
input wire i_dbus_ack); input wire i_dbus_ack);
localparam CSR_REGS = WITH_CSR*4; localparam CSR_REGS = WITH_CSR*4;
localparam RF_L2D = $clog2((32+CSR_REGS)*32/RF_WIDTH);
wire rf_wreq; wire rf_wreq;
wire rf_rreq; wire rf_rreq;

2
servant/servant_ram.v
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@ -32,7 +32,9 @@ module servant_ram
initial initial
if(|memfile) begin if(|memfile) begin
`ifndef ISE
$display("Preloading %m from %s", memfile); $display("Preloading %m from %s", memfile);
`endif
$readmemh(memfile, mem); $readmemh(memfile, mem);
end end