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Code Issues Releases Wiki Activity

Improve critical path in ctrl

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This commit is contained in:
Olof Kindgren
2019-01-12 22:33:31 +01:00
parent 813f9f4951
commit 3a68cc0e77
3 changed files with 16 additions and 15 deletions
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7
rtl/serv_ctrl.v
View File

@@ -10,7 +10,8 @@ module serv_ctrl
input wire i_offset,
input wire i_rs1,
input wire i_jalr,
input wire i_auipc,
input wire i_jal_or_jalr,
input wire i_utype,
input wire i_lui,
input wire i_trap,
input wire i_csr_pc,
@@ -70,9 +71,9 @@ module serv_ctrl
);
assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
assign o_rd = i_lui ? i_offset : i_auipc ? pc_plus_offset_aligned : pc_plus_4;
assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr);
assign offset_a = i_jalr ? i_rs1 : pc;
assign offset_a = !i_lui & (i_jalr ? i_rs1 : pc);
ser_add ser_add_pc_plus_offset
(

11
rtl/serv_decode.v
View File

@@ -14,7 +14,8 @@ module serv_decode
output wire o_ctrl_pc_en,
output reg o_ctrl_jump,
output wire o_ctrl_jalr,
output wire o_ctrl_auipc,
output wire o_ctrl_jal_or_jalr,
output wire o_ctrl_utype,
output wire o_ctrl_lui,
output wire o_ctrl_trap,
output wire o_ctrl_mret,
@@ -56,7 +57,6 @@ module serv_decode
output reg [2:0] o_funct3,
output wire o_imm,
output wire o_op_b_source,
output wire o_rd_ctrl_en,
output wire o_rd_alu_en,
output wire o_rd_mem_en);
@@ -119,10 +119,10 @@ module serv_decode
assign o_ctrl_pc_en = running | o_ctrl_trap;
wire take_branch = (opcode[4:2] == 3'b110) & (opcode[0] | i_alu_cmp);
assign o_ctrl_jalr = opcode[4] & (opcode[2:0] == 3'b001);
assign o_ctrl_auipc = !opcode[3] & opcode[2] & opcode[0];
assign o_ctrl_jalr = opcode[4] & (opcode[1:0] == 2'b01);
assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];
assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0];
assign o_ctrl_mret = (opcode[4] & opcode[2]) & op21 & !(|o_funct3);
assign o_rf_rd_en = running & (opcode[2] |
@@ -276,7 +276,6 @@ module serv_decode
//1 (OP_B_SOURCE_RS2) when BRANCH or OP
assign o_op_b_source = opcode[3];
assign o_rd_ctrl_en = opcode[0];
assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4];
assign o_rd_mem_en = !opcode[2] & !opcode[4];

13
rtl/serv_top.v
View File

@@ -51,7 +51,6 @@ module serv_top
wire [4:0] rs1_addr;
wire [4:0] rs2_addr;
wire rd_ctrl_en;
wire rd_alu_en;
wire rd_mem_en;
wire ctrl_rd;
@@ -65,7 +64,8 @@ module serv_top
wire ctrl_misalign;
wire jump;
wire jalr;
wire auipc;
wire jal_or_jalr;
wire utype;
wire mret;
wire imm;
wire trap;
@@ -143,7 +143,8 @@ module serv_top
.o_ctrl_pc_en (ctrl_pc_en),
.o_ctrl_jump (jump),
.o_ctrl_jalr (jalr),
.o_ctrl_auipc (auipc),
.o_ctrl_jal_or_jalr (jal_or_jalr),
.o_ctrl_utype (utype),
.o_ctrl_lui (lui),
.o_ctrl_trap (trap),
.o_ctrl_mret (mret),
@@ -185,7 +186,6 @@ module serv_top
.o_csr_d_sel (csr_d_sel),
.o_imm (imm),
.o_op_b_source (op_b_source),
.o_rd_ctrl_en (rd_ctrl_en),
.o_rd_alu_en (rd_alu_en),
.o_rd_mem_en (rd_mem_en));
@@ -202,7 +202,8 @@ module serv_top
.i_offset (imm),
.i_rs1 (rs1),
.i_jalr (jalr),
.i_auipc (auipc),
.i_jal_or_jalr (jal_or_jalr),
.i_utype (utype),
.i_lui (lui),
.i_trap (trap | mret),
.i_csr_pc (csr_rd),
@@ -213,7 +214,7 @@ module serv_top
.o_ibus_cyc (o_ibus_cyc),
.i_ibus_ack (i_ibus_ack));
assign rd = (rd_ctrl_en & ctrl_rd) |
assign rd = (ctrl_rd ) |
(rd_alu_en & alu_rd ) |
(csr_rd ) |
(rd_mem_en & mem_rd);