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Separate rf_ready and dbus_ack
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@@ -3,6 +3,7 @@ module serv_state
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input wire i_clk,
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input wire i_clk,
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input wire i_rst,
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input wire i_rst,
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input wire i_new_irq,
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input wire i_new_irq,
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input wire i_dbus_ack,
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input wire i_rf_ready,
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input wire i_rf_ready,
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input wire i_take_branch,
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input wire i_take_branch,
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input wire i_branch_op,
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input wire i_branch_op,
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@@ -102,7 +103,7 @@ module serv_state
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case (state)
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case (state)
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IDLE : begin
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IDLE : begin
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if (i_rf_ready) begin
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if (i_rf_ready | i_dbus_ack) begin
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state <= RUN;
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state <= RUN;
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if (two_stage_op & !stage_two_pending)
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if (two_stage_op & !stage_two_pending)
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state <= INIT;
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state <= INIT;
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@@ -140,7 +140,8 @@ module serv_top
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.i_clk (clk),
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.i_clk (clk),
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.i_rst (i_rst),
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.i_rst (i_rst),
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.i_new_irq (new_irq),
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.i_new_irq (new_irq),
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.i_rf_ready (rf_ready | i_dbus_ack),
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.i_dbus_ack (i_dbus_ack),
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.i_rf_ready (rf_ready),
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.i_take_branch (take_branch),
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.i_take_branch (take_branch),
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.i_branch_op (branch_op),
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.i_branch_op (branch_op),
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.i_mem_op (mem_op),
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.i_mem_op (mem_op),
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