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Add width and divider parameters to servant_timer

This commit is contained in:
Olof Kindgren
2019-11-19 10:20:34 +01:00
parent 1a961af5ac
commit 40e7855bac

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@@ -1,26 +1,31 @@
`default_nettype none
module servant_timer
#(parameter WIDTH = 16,
parameter DIVIDER = 0)
(input wire i_clk,
input wire i_rst,
output reg o_irq = 1'b0,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
output wire [31:0] o_wb_dat);
input wire i_rst,
output reg o_irq,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
output reg [31:0] o_wb_dat);
reg [15:0] mtime;
reg [15:0] mtimecmp;
localparam HIGH = WIDTH-1-DIVIDER;
assign o_wb_dat = {16'd0,mtime};
reg [WIDTH-1:0] mtime;
reg [HIGH:0] mtimecmp;
wire [HIGH:0] mtimeslice = mtime[WIDTH-1:DIVIDER];
always @(mtimeslice) begin
o_wb_dat = 32'd0;
o_wb_dat[HIGH:0] = mtimeslice;
end
always @(posedge i_clk) begin
if (i_wb_cyc & i_wb_we)
mtimecmp <= i_wb_dat[15:0];
mtime <= mtime + 16'd1;
o_irq <= (mtime >= mtimecmp);
if (i_rst) begin
mtime <= 16'd0;
mtimecmp <= 16'd0;
end
mtimecmp <= i_wb_dat[HIGH:0];
mtime <= mtime + 'd1;
o_irq <= (mtimeslice >= mtimecmp);
end
endmodule