Add nexys a7 support

data/nexys_a7.xdc

@@ -0,0 +1,4 @@
+set_property -dict {PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports i_clk];
+set_property -dict {PACKAGE_PIN D4  IOSTANDARD LVCMOS33 } [get_ports q]
+
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];

servant.core

@@ -4,9 +4,7 @@ name : ::servant:0
 
 filesets:
   service:
-    files:
-      - servant/ice40_pll.v
-      - servant/service.v
+    files: [servant/ice40_pll.v, servant/service.v]
     file_type : verilogSource
     depend : ["fusesoc:utils:generators"]
 
@@ -17,9 +15,7 @@ filesets:
     file_type : user
 
   servant_tb:
-    files:
-      - bench/servant_tb.v
-    file_type : verilogSource
+    files: [bench/servant_tb.v : {file_type : verilogSource}]
     depend : [vlog_tb_utils]
 
   soc:
@@ -35,9 +31,12 @@ filesets:
 
   tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
   icebreaker : {files: [data/icebreaker.pcf  : {file_type : PCF}]}
-
   verilator_tb: {files: [bench/servant_tb.cpp : {file_type : cppSource}]}
-
+  nexys_a7:
+    files:
+      - servant/servix_clock_gen.v : {file_type : verilogSource}
+      - servant/servix.v : {file_type : verilogSource}
+      - data/nexys_a7.xdc : {file_type : xdc}
 targets:
   default:
     filesets : [soc]
@@ -72,6 +71,14 @@ targets:
         mode : lint-only
     toplevel : servant
 
+  nexys_a7:
+    default_tool: vivado
+    filesets : [mem_files, soc, nexys_a7]
+    parameters : [memfile, memsize]
+    tools:
+      vivado: {part : xc7a100tcsg324-1}
+    toplevel : servix
+
   sim:
     default_tool: icarus
     filesets : [soc, servant_tb]

servant/servix.v

@@ -0,0 +1,27 @@
+`default_nettype none
+module servix
+(
+ input wire  i_clk,
+ output wire q);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+   parameter PLL = "NONE";
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   servix_clock_gen clock_gen
+     (.i_clk (i_clk),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule

servant/servix_clock_gen.v

@@ -0,0 +1,37 @@
+`default_nettype none
+module servix_clock_gen
+  (input wire  i_clk,
+   output wire o_clk,
+   output reg  o_rst);
+
+   wire   clkfb;
+   wire   locked;
+   reg 	  locked_r;
+
+   PLLE2_BASE
+     #(.BANDWIDTH("OPTIMIZED"),
+       .CLKFBOUT_MULT(16),
+       .CLKIN1_PERIOD(10.0), //100MHz
+       .CLKOUT0_DIVIDE(50),
+       .DIVCLK_DIVIDE(1),
+       .STARTUP_WAIT("FALSE"))
+   PLLE2_BASE_inst
+     (.CLKOUT0(o_clk),
+      .CLKOUT1(),
+      .CLKOUT2(),
+      .CLKOUT3(),
+      .CLKOUT4(),
+      .CLKOUT5(),
+      .CLKFBOUT(clkfb),
+      .LOCKED(locked),
+      .CLKIN1(i_clk),
+      .PWRDWN(1'b0),
+      .RST(1'b0),
+      .CLKFBIN(clkfb));
+
+   always @(posedge o_clk) begin
+      locked_r <= locked;
+      o_rst  <= !locked_r;
+   end
+
+endmodule