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Guarantee at least 2 cycles of o_rst after PLL locked.
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committed by
Olof Kindgren
parent
cb4276e8b2
commit
5cc7b0cbe1
@@ -11,8 +11,8 @@ module ice40_pll
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reg [1:0] rst_reg;
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reg [1:0] rst_reg;
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always @(posedge o_clk)
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always @(posedge o_clk)
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rst_reg <= {!locked, rst_reg[1]};
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rst_reg <= {rst_reg[0],locked};
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assign o_rst = rst_reg[0];
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assign o_rst = ~rst_reg[1];
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generate
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generate
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if (PLL == "ICE40_CORE") begin
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if (PLL == "ICE40_CORE") begin
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