Disable misalignment traps when CSR is disabled

rtl/serv_mem_if.v

@@ -1,5 +1,6 @@
 `default_nettype none
 module serv_mem_if
+  #(parameter WITH_CSR = 1)
   (
    input wire 	      i_clk,
    input wire 	      i_en,
@@ -20,7 +21,6 @@ module serv_mem_if
    input wire 	      i_wb_ack);
 
    reg           signbit;
-   reg 		 misalign;
 
    reg [7:0] 	 dat0;
    reg [7:0] 	 dat1;
@@ -57,8 +57,6 @@ module serv_mem_if
 
    assign o_wb_dat = {dat3,dat2,dat1,dat0};
 
-   assign o_misalign = misalign & i_mem_op;
-
    always @(posedge i_clk) begin
 
       if (dat0_en)
@@ -73,9 +71,18 @@ module serv_mem_if
       if (i_wb_ack)
 	{dat3,dat2,dat1,dat0} <= i_wb_rdt;
 
-      misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word);
       if (dat_valid)
         signbit <= dat_cur;
-
    end
+   generate
+      if (WITH_CSR) begin
+	 reg 		 misalign;
+	 always @(posedge i_clk)
+	   misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word);
+	 assign o_misalign = misalign & i_mem_op;
+      end else begin
+	 assign o_misalign = 1'b0;
+      end
+   endgenerate
+
 endmodule

rtl/serv_state.v

@@ -64,7 +64,7 @@ module serv_state
 
    assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !i_mem_misalign;
 
-   wire trap_pending = (o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign;
+   wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign);
 
    //Prepare RF for reads when a new instruction is fetched
    // or when stage one caused an exception (rreq implies a write request too)

rtl/serv_top.v

@@ -367,7 +367,9 @@ module serv_top
       //CSR read port
       .o_csr       (rf_csr_out));
 
-   serv_mem_if mem_if
+   serv_mem_if
+     #(.WITH_CSR (WITH_CSR))
+   mem_if
      (
       .i_clk    (clk),
       .i_en     (cnt_en),