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Add UART decoder

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This commit is contained in:
Olof Kindgren
2018-11-19 09:42:42 +01:00
parent f7b396601f
commit 6e034361d4
4 changed files with 68 additions and 15 deletions
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2
rtl/wb_gpio.v
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@@ -5,7 +5,7 @@ module wb_gpio
input wire i_wb_dat,
input wire i_wb_cyc,
output reg o_wb_ack,
output reg o_gpio = 1'b0);
output reg o_gpio = 1'b1);
always @(posedge i_wb_clk) begin
o_wb_ack <= 1'b0;