mirror of
https://github.com/olofk/serv.git
synced 2026-03-05 18:29:00 +00:00
Cleanup
This commit is contained in:
Olof Kindgren
43
barrel.mem
43
barrel.mem
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
8 imm_31_12
|
||||
7 imm_11_0
|
||||
6 rd
|
||||
5 rs2
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||||
4 rs1
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||||
3 funct3
|
||||
2 funct7
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||||
1 opcode
|
||||
0 halt
|
||||
*/
|
||||
000000001
|
||||
000000000
|
||||
000000010
|
||||
000000010
|
||||
000000010
|
||||
000000010
|
||||
000000010
|
||||
001000000
|
||||
001000000
|
||||
001000000
|
||||
001000000
|
||||
001000000
|
||||
100001000
|
||||
100001000
|
||||
100001000
|
||||
100010000
|
||||
100010000
|
||||
100010000
|
||||
100010000
|
||||
100010000
|
||||
110100000
|
||||
110100000
|
||||
110100000
|
||||
110100000
|
||||
110100000
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
43
decode.mem
43
decode.mem
@@ -1,43 +0,0 @@
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/*
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||||
8 imm_31_12
|
||||
7 imm_11_0
|
||||
6 rd
|
||||
5 rs2
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||||
4 rs1
|
||||
3 funct3
|
||||
2 funct7
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||||
1 opcode
|
||||
0 halt
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||||
*/
|
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000000001
|
||||
000000000
|
||||
000000010
|
||||
000000010
|
||||
000000010
|
||||
000000010
|
||||
000000010
|
||||
001000000
|
||||
001000000
|
||||
001000000
|
||||
001000000
|
||||
001000000
|
||||
100001000
|
||||
100001000
|
||||
100001000
|
||||
100010000
|
||||
100010000
|
||||
100010000
|
||||
100010000
|
||||
100010000
|
||||
110100000
|
||||
110100000
|
||||
110100000
|
||||
110100000
|
||||
110100000
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
110000100
|
||||
@@ -1,179 +0,0 @@
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|
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RISCV_GNU_TOOLCHAIN_GIT_REVISION = c3ad555
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||||
RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX = /opt/riscv32
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SHELL = bash
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TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
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FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve.o firmware/multest.o firmware/stats.o
|
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GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
|
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GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
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TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
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|
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# Add things like "export http_proxy=... https_proxy=..." here
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GIT_ENV = true
|
||||
|
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test: testbench.vvp firmware/firmware.hex
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vvp -N $<
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test_vcd: testbench.vvp firmware/firmware.hex
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vvp -N $< +vcd +trace +noerror
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|
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test_rvf: testbench_rvf.vvp firmware/firmware.hex
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vvp -N $< +vcd +trace +noerror
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test_wb: testbench_wb.vvp firmware/firmware.hex
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vvp -N $<
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|
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test_wb_vcd: testbench_wb.vvp firmware/firmware.hex
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vvp -N $< +vcd +trace +noerror
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test_ez: testbench_ez.vvp
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vvp -N $<
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test_ez_vcd: testbench_ez.vvp
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vvp -N $< +vcd
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|
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test_sp: testbench_sp.vvp firmware/firmware.hex
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vvp -N $<
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test_axi: testbench.vvp firmware/firmware.hex
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vvp -N $< +axi_test
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test_synth: testbench_synth.vvp firmware/firmware.hex
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vvp -N $<
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test_verilator: testbench_verilator firmware/firmware.hex
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./testbench_verilator
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testbench.vvp: testbench.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_rvf.vvp: testbench.v picorv32.v rvfimon.v
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iverilog -o $@ -D RISCV_FORMAL $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_wb.vvp: testbench_wb.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_ez.vvp: testbench_ez.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_sp.vvp: testbench.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^
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chmod -x $@
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testbench_synth.vvp: testbench.v synth.v
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iverilog -o $@ -DSYNTH_TEST $^
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chmod -x $@
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testbench_verilator: testbench.v picorv32.v
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verilator --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench.v picorv32.v testbench.cc \
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$(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) --Mdir testbench_verilator_dir
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$(MAKE) -C testbench_verilator_dir -f Vpicorv32_wrapper.mk
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cp testbench_verilator_dir/Vpicorv32_wrapper testbench_verilator
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check: check-yices
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check-%: check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
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|
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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-p 'prep -top picorv32 -nordff' \
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-p 'assertpmux -noinit; opt -fast' \
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||||
-p 'write_smt2 -wires check.smt2'
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||||
|
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synth.v: picorv32.v scripts/yosys/synth_sim.ys
|
||||
yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
|
||||
|
||||
firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
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||||
python3 firmware/makehex.py $< 16384 > $@
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||||
|
||||
firmware/firmware.bin: firmware/firmware.elf
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||||
$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
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chmod -x $@
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||||
|
||||
firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
|
||||
$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o $@ \
|
||||
-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
|
||||
$(FIRMWARE_OBJS) $(TEST_OBJS) -lgcc
|
||||
chmod -x $@
|
||||
|
||||
firmware/start.o: firmware/start.S
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||||
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
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||||
|
||||
firmware/%.o: firmware/%.c
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||||
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
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||||
|
||||
tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
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||||
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
|
||||
-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
|
||||
|
||||
download-tools:
|
||||
sudo bash -c 'set -ex; mkdir -p /var/cache/distfiles; $(GIT_ENV); \
|
||||
$(foreach REPO,riscv-gnu-toolchain riscv-binutils-gdb riscv-dejagnu riscv-gcc riscv-glibc riscv-newlib riscv-qemu, \
|
||||
if ! test -d /var/cache/distfiles/$(REPO).git; then rm -rf /var/cache/distfiles/$(REPO).git.part; \
|
||||
git clone --bare https://github.com/riscv/$(REPO) /var/cache/distfiles/$(REPO).git.part; \
|
||||
mv /var/cache/distfiles/$(REPO).git.part /var/cache/distfiles/$(REPO).git; else \
|
||||
(cd /var/cache/distfiles/$(REPO).git; git fetch https://github.com/riscv/$(REPO)); fi;)'
|
||||
|
||||
define build_tools_template
|
||||
build-$(1)-tools:
|
||||
@read -p "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)). Type YES to continue: " reply && [[ "$$$$reply" == [Yy][Ee][Ss] || "$$$$reply" == [Yy] ]]
|
||||
sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); chown $$$${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1))"
|
||||
+$(MAKE) build-$(1)-tools-bh
|
||||
|
||||
build-$(1)-tools-bh:
|
||||
+set -ex; $(GIT_ENV); \
|
||||
if [ -d /var/cache/distfiles/riscv-gnu-toolchain.git ]; then reference_riscv_gnu_toolchain="--reference /var/cache/distfiles/riscv-gnu-toolchain.git"; else reference_riscv_gnu_toolchain=""; fi; \
|
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if [ -d /var/cache/distfiles/riscv-binutils-gdb.git ]; then reference_riscv_binutils_gdb="--reference /var/cache/distfiles/riscv-binutils-gdb.git"; else reference_riscv_binutils_gdb=""; fi; \
|
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if [ -d /var/cache/distfiles/riscv-dejagnu.git ]; then reference_riscv_dejagnu="--reference /var/cache/distfiles/riscv-dejagnu.git"; else reference_riscv_dejagnu=""; fi; \
|
||||
if [ -d /var/cache/distfiles/riscv-gcc.git ]; then reference_riscv_gcc="--reference /var/cache/distfiles/riscv-gcc.git"; else reference_riscv_gcc=""; fi; \
|
||||
if [ -d /var/cache/distfiles/riscv-glibc.git ]; then reference_riscv_glibc="--reference /var/cache/distfiles/riscv-glibc.git"; else reference_riscv_glibc=""; fi; \
|
||||
if [ -d /var/cache/distfiles/riscv-newlib.git ]; then reference_riscv_newlib="--reference /var/cache/distfiles/riscv-newlib.git"; else reference_riscv_newlib=""; fi; \
|
||||
if [ -d /var/cache/distfiles/riscv-qemu.git ]; then reference_riscv_qemu="--reference /var/cache/distfiles/riscv-qemu.git"; else reference_riscv_qemu=""; fi; \
|
||||
rm -rf riscv-gnu-toolchain-$(1); git clone $$$$reference_riscv_gnu_toolchain https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-$(1); \
|
||||
cd riscv-gnu-toolchain-$(1); git checkout $(RISCV_GNU_TOOLCHAIN_GIT_REVISION); \
|
||||
git submodule update --init $$$$reference_riscv_binutils_gdb riscv-binutils; \
|
||||
git submodule update --init $$$$reference_riscv_binutils_gdb riscv-gdb; \
|
||||
git submodule update --init $$$$reference_riscv_dejagnu riscv-dejagnu; \
|
||||
git submodule update --init $$$$reference_riscv_gcc riscv-gcc; \
|
||||
git submodule update --init $$$$reference_riscv_glibc riscv-glibc; \
|
||||
git submodule update --init $$$$reference_riscv_newlib riscv-newlib; \
|
||||
git submodule update --init $$$$reference_riscv_qemu riscv-qemu; \
|
||||
mkdir build; cd build; ../configure --with-arch=$(2) --prefix=$(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); make
|
||||
|
||||
.PHONY: build-$(1)-tools
|
||||
endef
|
||||
|
||||
$(eval $(call build_tools_template,riscv32i,rv32i))
|
||||
$(eval $(call build_tools_template,riscv32ic,rv32ic))
|
||||
$(eval $(call build_tools_template,riscv32im,rv32im))
|
||||
$(eval $(call build_tools_template,riscv32imc,rv32imc))
|
||||
|
||||
build-tools:
|
||||
@echo "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)ic, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)im, and $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)imc."
|
||||
@read -p "Type YES to continue: " reply && [[ "$$reply" == [Yy][Ee][Ss] || "$$reply" == [Yy] ]]
|
||||
sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; chown $${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}"
|
||||
+$(MAKE) build-riscv32i-tools-bh
|
||||
+$(MAKE) build-riscv32ic-tools-bh
|
||||
+$(MAKE) build-riscv32im-tools-bh
|
||||
+$(MAKE) build-riscv32imc-tools-bh
|
||||
|
||||
toc:
|
||||
gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
|
||||
|
||||
clean:
|
||||
rm -rf riscv-gnu-toolchain-riscv32i riscv-gnu-toolchain-riscv32ic \
|
||||
riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
|
||||
rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
|
||||
firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
|
||||
testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
|
||||
testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace \
|
||||
testbench_verilator testbench_verilator_dir
|
||||
|
||||
.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean
|
||||
@@ -1,2 +0,0 @@
|
||||
A simple test firmware. This code is in the public domain. Simply copy whatever
|
||||
you can use.
|
||||
@@ -1,102 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#define regnum_q0 0
|
||||
#define regnum_q1 1
|
||||
#define regnum_q2 2
|
||||
#define regnum_q3 3
|
||||
|
||||
#define regnum_x0 0
|
||||
#define regnum_x1 1
|
||||
#define regnum_x2 2
|
||||
#define regnum_x3 3
|
||||
#define regnum_x4 4
|
||||
#define regnum_x5 5
|
||||
#define regnum_x6 6
|
||||
#define regnum_x7 7
|
||||
#define regnum_x8 8
|
||||
#define regnum_x9 9
|
||||
#define regnum_x10 10
|
||||
#define regnum_x11 11
|
||||
#define regnum_x12 12
|
||||
#define regnum_x13 13
|
||||
#define regnum_x14 14
|
||||
#define regnum_x15 15
|
||||
#define regnum_x16 16
|
||||
#define regnum_x17 17
|
||||
#define regnum_x18 18
|
||||
#define regnum_x19 19
|
||||
#define regnum_x20 20
|
||||
#define regnum_x21 21
|
||||
#define regnum_x22 22
|
||||
#define regnum_x23 23
|
||||
#define regnum_x24 24
|
||||
#define regnum_x25 25
|
||||
#define regnum_x26 26
|
||||
#define regnum_x27 27
|
||||
#define regnum_x28 28
|
||||
#define regnum_x29 29
|
||||
#define regnum_x30 30
|
||||
#define regnum_x31 31
|
||||
|
||||
#define regnum_zero 0
|
||||
#define regnum_ra 1
|
||||
#define regnum_sp 2
|
||||
#define regnum_gp 3
|
||||
#define regnum_tp 4
|
||||
#define regnum_t0 5
|
||||
#define regnum_t1 6
|
||||
#define regnum_t2 7
|
||||
#define regnum_s0 8
|
||||
#define regnum_s1 9
|
||||
#define regnum_a0 10
|
||||
#define regnum_a1 11
|
||||
#define regnum_a2 12
|
||||
#define regnum_a3 13
|
||||
#define regnum_a4 14
|
||||
#define regnum_a5 15
|
||||
#define regnum_a6 16
|
||||
#define regnum_a7 17
|
||||
#define regnum_s2 18
|
||||
#define regnum_s3 19
|
||||
#define regnum_s4 20
|
||||
#define regnum_s5 21
|
||||
#define regnum_s6 22
|
||||
#define regnum_s7 23
|
||||
#define regnum_s8 24
|
||||
#define regnum_s9 25
|
||||
#define regnum_s10 26
|
||||
#define regnum_s11 27
|
||||
#define regnum_t3 28
|
||||
#define regnum_t4 29
|
||||
#define regnum_t5 30
|
||||
#define regnum_t6 31
|
||||
|
||||
// x8 is s0 and also fp
|
||||
#define regnum_fp 8
|
||||
|
||||
#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
|
||||
.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
|
||||
|
||||
#define picorv32_getq_insn(_rd, _qs) \
|
||||
r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
|
||||
|
||||
#define picorv32_setq_insn(_qd, _rs) \
|
||||
r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
|
||||
|
||||
#define picorv32_retirq_insn() \
|
||||
r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
|
||||
|
||||
#define picorv32_maskirq_insn(_rd, _rs) \
|
||||
r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
|
||||
|
||||
#define picorv32_waitirq_insn(_rd) \
|
||||
r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
|
||||
|
||||
#define picorv32_timer_insn(_rd, _rs) \
|
||||
r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
|
||||
|
||||
Binary file not shown.
@@ -1,36 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#ifndef FIRMWARE_H
|
||||
#define FIRMWARE_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
// irq.c
|
||||
uint32_t *irq(uint32_t *regs, uint32_t irqs);
|
||||
|
||||
// print.c
|
||||
void print_chr(char ch);
|
||||
void print_str(const char *p);
|
||||
void print_dec(unsigned int val);
|
||||
void print_hex(unsigned int val, int digits);
|
||||
|
||||
// sieve.c
|
||||
void sieve(void);
|
||||
|
||||
// multest.c
|
||||
uint32_t hard_mul(uint32_t a, uint32_t b);
|
||||
uint32_t hard_mulh(uint32_t a, uint32_t b);
|
||||
uint32_t hard_mulhsu(uint32_t a, uint32_t b);
|
||||
uint32_t hard_mulhu(uint32_t a, uint32_t b);
|
||||
void multest(void);
|
||||
|
||||
// stats.c
|
||||
void stats(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,140 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#include "firmware.h"
|
||||
|
||||
uint32_t *irq(uint32_t *regs, uint32_t irqs)
|
||||
{
|
||||
static unsigned int ext_irq_4_count = 0;
|
||||
static unsigned int ext_irq_5_count = 0;
|
||||
static unsigned int timer_irq_count = 0;
|
||||
|
||||
// checking compressed isa q0 reg handling
|
||||
if ((irqs & 6) != 0) {
|
||||
uint32_t pc = (regs[0] & 1) ? regs[0] - 3 : regs[0] - 4;
|
||||
uint32_t instr = *(uint16_t*)pc;
|
||||
|
||||
if ((instr & 3) == 3)
|
||||
instr = instr | (*(uint16_t*)(pc + 2)) << 16;
|
||||
|
||||
if (((instr & 3) != 3) != (regs[0] & 1)) {
|
||||
print_str("Mismatch between q0 LSB and decoded instruction word! q0=0x");
|
||||
print_hex(regs[0], 8);
|
||||
print_str(", instr=0x");
|
||||
if ((instr & 3) == 3)
|
||||
print_hex(instr, 8);
|
||||
else
|
||||
print_hex(instr, 4);
|
||||
print_str("\n");
|
||||
__asm__ volatile ("ebreak");
|
||||
}
|
||||
}
|
||||
|
||||
if ((irqs & (1<<4)) != 0) {
|
||||
ext_irq_4_count++;
|
||||
// print_str("[EXT-IRQ-4]");
|
||||
}
|
||||
|
||||
if ((irqs & (1<<5)) != 0) {
|
||||
ext_irq_5_count++;
|
||||
// print_str("[EXT-IRQ-5]");
|
||||
}
|
||||
|
||||
if ((irqs & 1) != 0) {
|
||||
timer_irq_count++;
|
||||
// print_str("[TIMER-IRQ]");
|
||||
}
|
||||
|
||||
if ((irqs & 6) != 0)
|
||||
{
|
||||
uint32_t pc = (regs[0] & 1) ? regs[0] - 3 : regs[0] - 4;
|
||||
uint32_t instr = *(uint16_t*)pc;
|
||||
|
||||
if ((instr & 3) == 3)
|
||||
instr = instr | (*(uint16_t*)(pc + 2)) << 16;
|
||||
|
||||
print_str("\n");
|
||||
print_str("------------------------------------------------------------\n");
|
||||
|
||||
if ((irqs & 2) != 0) {
|
||||
if (instr == 0x00100073 || instr == 0x9002) {
|
||||
print_str("EBREAK instruction at 0x");
|
||||
print_hex(pc, 8);
|
||||
print_str("\n");
|
||||
} else {
|
||||
print_str("Illegal Instruction at 0x");
|
||||
print_hex(pc, 8);
|
||||
print_str(": 0x");
|
||||
print_hex(instr, ((instr & 3) == 3) ? 8 : 4);
|
||||
print_str("\n");
|
||||
}
|
||||
}
|
||||
|
||||
if ((irqs & 4) != 0) {
|
||||
print_str("Bus error in Instruction at 0x");
|
||||
print_hex(pc, 8);
|
||||
print_str(": 0x");
|
||||
print_hex(instr, ((instr & 3) == 3) ? 8 : 4);
|
||||
print_str("\n");
|
||||
}
|
||||
|
||||
for (int i = 0; i < 8; i++)
|
||||
for (int k = 0; k < 4; k++)
|
||||
{
|
||||
int r = i + k*8;
|
||||
|
||||
if (r == 0) {
|
||||
print_str("pc ");
|
||||
} else
|
||||
if (r < 10) {
|
||||
print_chr('x');
|
||||
print_chr('0' + r);
|
||||
print_chr(' ');
|
||||
print_chr(' ');
|
||||
} else
|
||||
if (r < 20) {
|
||||
print_chr('x');
|
||||
print_chr('1');
|
||||
print_chr('0' + r - 10);
|
||||
print_chr(' ');
|
||||
} else
|
||||
if (r < 30) {
|
||||
print_chr('x');
|
||||
print_chr('2');
|
||||
print_chr('0' + r - 20);
|
||||
print_chr(' ');
|
||||
} else {
|
||||
print_chr('x');
|
||||
print_chr('3');
|
||||
print_chr('0' + r - 30);
|
||||
print_chr(' ');
|
||||
}
|
||||
|
||||
print_hex(regs[r], 8);
|
||||
print_str(k == 3 ? "\n" : " ");
|
||||
}
|
||||
|
||||
print_str("------------------------------------------------------------\n");
|
||||
|
||||
print_str("Number of fast external IRQs counted: ");
|
||||
print_dec(ext_irq_4_count);
|
||||
print_str("\n");
|
||||
|
||||
print_str("Number of slow external IRQs counted: ");
|
||||
print_dec(ext_irq_5_count);
|
||||
print_str("\n");
|
||||
|
||||
print_str("Number of timer IRQs counted: ");
|
||||
print_dec(timer_irq_count);
|
||||
print_str("\n");
|
||||
|
||||
__asm__ volatile ("ebreak");
|
||||
}
|
||||
|
||||
return regs;
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -1,27 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
#
|
||||
# This is free and unencumbered software released into the public domain.
|
||||
#
|
||||
# Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
# distribute this software, either in source code form or as a compiled
|
||||
# binary, for any purpose, commercial or non-commercial, and by any
|
||||
# means.
|
||||
|
||||
from sys import argv
|
||||
|
||||
binfile = argv[1]
|
||||
nwords = int(argv[2])
|
||||
|
||||
with open(binfile, "rb") as f:
|
||||
bindata = f.read()
|
||||
|
||||
assert len(bindata) < 4*nwords
|
||||
assert len(bindata) % 4 == 0
|
||||
|
||||
for i in range(nwords):
|
||||
if i < len(bindata) // 4:
|
||||
w = bindata[4*i : 4*i+4]
|
||||
print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0]))
|
||||
else:
|
||||
print("0")
|
||||
|
||||
@@ -1,85 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#include "firmware.h"
|
||||
|
||||
static uint32_t xorshift32(void) {
|
||||
static uint32_t x = 314159265;
|
||||
x ^= x << 13;
|
||||
x ^= x >> 17;
|
||||
x ^= x << 5;
|
||||
return x;
|
||||
}
|
||||
|
||||
void multest(void)
|
||||
{
|
||||
for (int i = 0; i < 10; i++)
|
||||
{
|
||||
uint32_t a = xorshift32();
|
||||
uint32_t b = xorshift32();
|
||||
|
||||
uint64_t au = a, bu = b;
|
||||
int64_t as = (int32_t)a, bs = (int32_t)b;
|
||||
|
||||
print_str("input [");
|
||||
print_hex(as >> 32, 8);
|
||||
print_str("] ");
|
||||
print_hex(a, 8);
|
||||
print_str(" [");
|
||||
print_hex(bs >> 32, 8);
|
||||
print_str("] ");
|
||||
print_hex(b, 8);
|
||||
print_chr('\n');
|
||||
|
||||
//uint32_t h_mul, h_mulh, h_mulhsu, h_mulhu;
|
||||
print_str("hard ");
|
||||
|
||||
//h_mul = hard_mul(a, b);
|
||||
//print_hex(h_mul, 8);
|
||||
//print_str(" ");
|
||||
|
||||
//h_mulh = hard_mulh(a, b);
|
||||
//print_hex(h_mulh, 8);
|
||||
//print_str(" ");
|
||||
|
||||
//h_mulhsu = hard_mulhsu(a, b);
|
||||
//print_hex(h_mulhsu, 8);
|
||||
//print_str(" ");
|
||||
|
||||
// h_mulhu = hard_mulhu(a, b);
|
||||
//print_hex(h_mulhu, 8);
|
||||
//print_chr('\n');
|
||||
|
||||
uint32_t s_mul, s_mulh, s_mulhsu, s_mulhu;
|
||||
print_str("soft ");
|
||||
|
||||
s_mul = a * b;
|
||||
print_hex(s_mul, 8);
|
||||
print_str(" ");
|
||||
|
||||
s_mulh = (as * bs) >> 32;
|
||||
print_hex(s_mulh, 8);
|
||||
print_str(" ");
|
||||
|
||||
s_mulhsu = (as * bu) >> 32;
|
||||
print_hex(s_mulhsu, 8);
|
||||
print_str(" ");
|
||||
|
||||
s_mulhu = (au * bu) >> 32;
|
||||
print_hex(s_mulhu, 8);
|
||||
print_str(" ");
|
||||
|
||||
/*if (s_mul != h_mul || s_mulh != h_mulh || s_mulhsu != h_mulhsu || s_mulhu != h_mulhu) {
|
||||
print_str("ERROR!\n");
|
||||
__asm__ volatile ("ebreak");
|
||||
return;
|
||||
}*/
|
||||
|
||||
print_str(" OK\n");
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,41 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#include "firmware.h"
|
||||
|
||||
#define OUTPORT 0x10000000
|
||||
|
||||
void print_chr(char ch)
|
||||
{
|
||||
*((volatile uint32_t*)OUTPORT) = ch;
|
||||
}
|
||||
|
||||
void print_str(const char *p)
|
||||
{
|
||||
while (*p != 0)
|
||||
*((volatile uint32_t*)OUTPORT) = *(p++);
|
||||
}
|
||||
|
||||
void print_dec(unsigned int val)
|
||||
{
|
||||
char buffer[10];
|
||||
char *p = buffer;
|
||||
while (val || p == buffer) {
|
||||
*(p++) = val % 10;
|
||||
val = val / 10;
|
||||
}
|
||||
while (p != buffer) {
|
||||
*((volatile uint32_t*)OUTPORT) = '0' + *(--p);
|
||||
}
|
||||
}
|
||||
|
||||
void print_hex(unsigned int val, int digits)
|
||||
{
|
||||
for (int i = (4*digits)-4; i >= 0; i -= 4)
|
||||
*((volatile uint32_t*)OUTPORT) = "0123456789ABCDEF"[(val >> i) % 16];
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -1,200 +0,0 @@
|
||||
/* ---- Original Script: /opt/riscv32i/riscv32-unknown-elf/lib/ldscripts/elf32lriscv.x ---- */
|
||||
/* Default linker script, for normal executables */
|
||||
/* Copyright (C) 2014-2017 Free Software Foundation, Inc.
|
||||
Copying and distribution of this script, with or without modification,
|
||||
are permitted in any medium without royalty provided the copyright
|
||||
notice and this notice are preserved. */
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
|
||||
"elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00010000;
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
|
||||
*(.text.exit .text.exit.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text.hot .text.hot.*)
|
||||
*(.stub .text.* .gnu.linkonce.t.*)
|
||||
/* .gnu.warning sections are handled specially by elf32.em. */
|
||||
*(.gnu.warning)
|
||||
}
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
}
|
||||
.plt : { *(.plt) }
|
||||
.iplt : { *(.iplt) }
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
}
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
|
||||
.rodata1 : { *(.rodata1) }
|
||||
.sdata2 :
|
||||
{
|
||||
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
|
||||
}
|
||||
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) }
|
||||
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table
|
||||
.gcc_except_table.*) }
|
||||
.gnu_extab : ONLY_IF_RO { *(.gnu_extab*) }
|
||||
/* These sections are generated by the Sun/Oracle C++ compiler. */
|
||||
.exception_ranges : ONLY_IF_RO { *(.exception_ranges
|
||||
.exception_ranges*) }
|
||||
/* Adjust the address for the data segment. We want to adjust up to
|
||||
the same address within the page on the next page up. */
|
||||
. = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
|
||||
/* Exception handling */
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) }
|
||||
.gnu_extab : ONLY_IF_RW { *(.gnu_extab) }
|
||||
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
|
||||
.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) }
|
||||
/* Thread Local Storage sections */
|
||||
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
|
||||
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
}
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
}
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
}
|
||||
.jcr : { KEEP (*(.jcr)) }
|
||||
.data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
|
||||
.dynamic : { *(.dynamic) }
|
||||
. = DATA_SEGMENT_RELRO_END (0, .);
|
||||
.data :
|
||||
{
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
SORT(CONSTRUCTORS)
|
||||
}
|
||||
.data1 : { *(.data1) }
|
||||
.got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
|
||||
/* We want the small data sections together, so single-instruction offsets
|
||||
can access them all, and initialized data all before uninitialized, so
|
||||
we can shorten the on-disk segment size. */
|
||||
.sdata :
|
||||
{
|
||||
__global_pointer$ = . + 0x800;
|
||||
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|
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|
||||
Copying and distribution of this script, with or without modification,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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||||
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||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
/* DWARF 3 */
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
This is free and unencumbered software released into the public domain.
|
||||
|
||||
Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
distribute this software, either in source code form or as a compiled
|
||||
binary, for any purpose, commercial or non-commercial, and by any
|
||||
means.
|
||||
*/
|
||||
|
||||
MEMORY {
|
||||
/* the memory in the testbench is 64k in size;
|
||||
* set LENGTH=48k and leave at least 16k for stack */
|
||||
mem : ORIGIN = 0x00000000, LENGTH = 0x0000c000
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
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|
||||
. = 0x000000;
|
||||
start*(.text);
|
||||
*(.text);
|
||||
*(*);
|
||||
end = .;
|
||||
} > mem
|
||||
}
|
||||
@@ -1,84 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
// A simple Sieve of Eratosthenes
|
||||
|
||||
#include "firmware.h"
|
||||
|
||||
#define BITMAP_SIZE 64
|
||||
|
||||
static uint32_t bitmap[BITMAP_SIZE/32];
|
||||
static uint32_t hash;
|
||||
|
||||
static uint32_t mkhash(uint32_t a, uint32_t b)
|
||||
{
|
||||
// The XOR version of DJB2
|
||||
return ((a << 5) + a) ^ b;
|
||||
}
|
||||
|
||||
static void bitmap_set(int idx)
|
||||
{
|
||||
bitmap[idx/32] |= 1 << (idx % 32);
|
||||
}
|
||||
|
||||
static bool bitmap_get(int idx)
|
||||
{
|
||||
return (bitmap[idx/32] & (1 << (idx % 32))) != 0;
|
||||
}
|
||||
|
||||
static void print_prime(int idx, int val)
|
||||
{
|
||||
if (idx < 10)
|
||||
print_str(" ");
|
||||
print_dec(idx);
|
||||
if (idx / 10 == 1)
|
||||
goto force_th;
|
||||
switch (idx % 10) {
|
||||
case 1: print_str("st"); break;
|
||||
case 2: print_str("nd"); break;
|
||||
case 3: print_str("rd"); break;
|
||||
force_th:
|
||||
default: print_str("th"); break;
|
||||
}
|
||||
print_str(" prime is ");
|
||||
print_dec(val);
|
||||
print_str(".\n");
|
||||
|
||||
hash = mkhash(hash, idx);
|
||||
hash = mkhash(hash, val);
|
||||
}
|
||||
|
||||
void sieve(void)
|
||||
{
|
||||
int idx = 1;
|
||||
hash = 5381;
|
||||
print_prime(idx++, 2);
|
||||
for (int i = 0; i < BITMAP_SIZE; i++) {
|
||||
if (bitmap_get(i))
|
||||
continue;
|
||||
print_prime(idx++, 3+2*i);
|
||||
for (int j = 2*(3+2*i);; j += 3+2*i) {
|
||||
if (j%2 == 0)
|
||||
continue;
|
||||
int k = (j-3)/2;
|
||||
if (k >= BITMAP_SIZE)
|
||||
break;
|
||||
bitmap_set(k);
|
||||
}
|
||||
}
|
||||
|
||||
print_str("checksum: ");
|
||||
print_hex(hash, 8);
|
||||
|
||||
if (hash == 0x1772A48F) {
|
||||
print_str(" OK\n");
|
||||
} else {
|
||||
print_str(" ERROR\n");
|
||||
__asm__ volatile ("ebreak");
|
||||
}
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -1,507 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#define ENABLE_QREGS
|
||||
#define ENABLE_RVTST
|
||||
#define ENABLE_SIEVE
|
||||
//#define ENABLE_MULTST
|
||||
#define ENABLE_STATS
|
||||
|
||||
#ifndef ENABLE_QREGS
|
||||
# undef ENABLE_RVTST
|
||||
#endif
|
||||
|
||||
// Only save registers in IRQ wrapper that are to be saved by the caller in
|
||||
// the RISC-V ABI, with the excpetion of the stack pointer. The IRQ handler
|
||||
// will save the rest if necessary. I.e. skip x3, x4, x8, x9, and x18-x27.
|
||||
#undef ENABLE_FASTIRQ
|
||||
|
||||
#include "custom_ops.S"
|
||||
|
||||
.section .text
|
||||
.global irq
|
||||
.global sieve
|
||||
.global multest
|
||||
.global hard_mul
|
||||
.global hard_mulh
|
||||
.global hard_mulhsu
|
||||
.global hard_mulhu
|
||||
.global stats
|
||||
|
||||
reset_vec:
|
||||
// no more than 16 bytes here !
|
||||
picorv32_waitirq_insn(zero)
|
||||
picorv32_maskirq_insn(zero, zero)
|
||||
j start
|
||||
|
||||
|
||||
/* Interrupt handler
|
||||
**********************************/
|
||||
|
||||
.balign 16
|
||||
irq_vec:
|
||||
/* save registers */
|
||||
|
||||
#ifdef ENABLE_QREGS
|
||||
|
||||
picorv32_setq_insn(q2, x1)
|
||||
picorv32_setq_insn(q3, x2)
|
||||
|
||||
lui x1, %hi(irq_regs)
|
||||
addi x1, x1, %lo(irq_regs)
|
||||
|
||||
picorv32_getq_insn(x2, q0)
|
||||
sw x2, 0*4(x1)
|
||||
|
||||
picorv32_getq_insn(x2, q2)
|
||||
sw x2, 1*4(x1)
|
||||
|
||||
picorv32_getq_insn(x2, q3)
|
||||
sw x2, 2*4(x1)
|
||||
|
||||
#ifdef ENABLE_FASTIRQ
|
||||
sw x5, 5*4(x1)
|
||||
sw x6, 6*4(x1)
|
||||
sw x7, 7*4(x1)
|
||||
sw x10, 10*4(x1)
|
||||
sw x11, 11*4(x1)
|
||||
sw x12, 12*4(x1)
|
||||
sw x13, 13*4(x1)
|
||||
sw x14, 14*4(x1)
|
||||
sw x15, 15*4(x1)
|
||||
sw x16, 16*4(x1)
|
||||
sw x17, 17*4(x1)
|
||||
sw x28, 28*4(x1)
|
||||
sw x29, 29*4(x1)
|
||||
sw x30, 30*4(x1)
|
||||
sw x31, 31*4(x1)
|
||||
#else
|
||||
sw x3, 3*4(x1)
|
||||
sw x4, 4*4(x1)
|
||||
sw x5, 5*4(x1)
|
||||
sw x6, 6*4(x1)
|
||||
sw x7, 7*4(x1)
|
||||
sw x8, 8*4(x1)
|
||||
sw x9, 9*4(x1)
|
||||
sw x10, 10*4(x1)
|
||||
sw x11, 11*4(x1)
|
||||
sw x12, 12*4(x1)
|
||||
sw x13, 13*4(x1)
|
||||
sw x14, 14*4(x1)
|
||||
sw x15, 15*4(x1)
|
||||
sw x16, 16*4(x1)
|
||||
sw x17, 17*4(x1)
|
||||
sw x18, 18*4(x1)
|
||||
sw x19, 19*4(x1)
|
||||
sw x20, 20*4(x1)
|
||||
sw x21, 21*4(x1)
|
||||
sw x22, 22*4(x1)
|
||||
sw x23, 23*4(x1)
|
||||
sw x24, 24*4(x1)
|
||||
sw x25, 25*4(x1)
|
||||
sw x26, 26*4(x1)
|
||||
sw x27, 27*4(x1)
|
||||
sw x28, 28*4(x1)
|
||||
sw x29, 29*4(x1)
|
||||
sw x30, 30*4(x1)
|
||||
sw x31, 31*4(x1)
|
||||
#endif
|
||||
|
||||
#else // ENABLE_QREGS
|
||||
|
||||
#ifdef ENABLE_FASTIRQ
|
||||
sw gp, 0*4+0x200(zero)
|
||||
sw x1, 1*4+0x200(zero)
|
||||
sw x2, 2*4+0x200(zero)
|
||||
sw x5, 5*4+0x200(zero)
|
||||
sw x6, 6*4+0x200(zero)
|
||||
sw x7, 7*4+0x200(zero)
|
||||
sw x10, 10*4+0x200(zero)
|
||||
sw x11, 11*4+0x200(zero)
|
||||
sw x12, 12*4+0x200(zero)
|
||||
sw x13, 13*4+0x200(zero)
|
||||
sw x14, 14*4+0x200(zero)
|
||||
sw x15, 15*4+0x200(zero)
|
||||
sw x16, 16*4+0x200(zero)
|
||||
sw x17, 17*4+0x200(zero)
|
||||
sw x28, 28*4+0x200(zero)
|
||||
sw x29, 29*4+0x200(zero)
|
||||
sw x30, 30*4+0x200(zero)
|
||||
sw x31, 31*4+0x200(zero)
|
||||
#else
|
||||
sw gp, 0*4+0x200(zero)
|
||||
sw x1, 1*4+0x200(zero)
|
||||
sw x2, 2*4+0x200(zero)
|
||||
sw x3, 3*4+0x200(zero)
|
||||
sw x4, 4*4+0x200(zero)
|
||||
sw x5, 5*4+0x200(zero)
|
||||
sw x6, 6*4+0x200(zero)
|
||||
sw x7, 7*4+0x200(zero)
|
||||
sw x8, 8*4+0x200(zero)
|
||||
sw x9, 9*4+0x200(zero)
|
||||
sw x10, 10*4+0x200(zero)
|
||||
sw x11, 11*4+0x200(zero)
|
||||
sw x12, 12*4+0x200(zero)
|
||||
sw x13, 13*4+0x200(zero)
|
||||
sw x14, 14*4+0x200(zero)
|
||||
sw x15, 15*4+0x200(zero)
|
||||
sw x16, 16*4+0x200(zero)
|
||||
sw x17, 17*4+0x200(zero)
|
||||
sw x18, 18*4+0x200(zero)
|
||||
sw x19, 19*4+0x200(zero)
|
||||
sw x20, 20*4+0x200(zero)
|
||||
sw x21, 21*4+0x200(zero)
|
||||
sw x22, 22*4+0x200(zero)
|
||||
sw x23, 23*4+0x200(zero)
|
||||
sw x24, 24*4+0x200(zero)
|
||||
sw x25, 25*4+0x200(zero)
|
||||
sw x26, 26*4+0x200(zero)
|
||||
sw x27, 27*4+0x200(zero)
|
||||
sw x28, 28*4+0x200(zero)
|
||||
sw x29, 29*4+0x200(zero)
|
||||
sw x30, 30*4+0x200(zero)
|
||||
sw x31, 31*4+0x200(zero)
|
||||
#endif
|
||||
|
||||
#endif // ENABLE_QREGS
|
||||
|
||||
/* call interrupt handler C function */
|
||||
|
||||
lui sp, %hi(irq_stack)
|
||||
addi sp, sp, %lo(irq_stack)
|
||||
|
||||
// arg0 = address of regs
|
||||
lui a0, %hi(irq_regs)
|
||||
addi a0, a0, %lo(irq_regs)
|
||||
|
||||
// arg1 = interrupt type
|
||||
#ifdef ENABLE_QREGS
|
||||
picorv32_getq_insn(a1, q1)
|
||||
#else
|
||||
addi a1, tp, 0
|
||||
#endif
|
||||
|
||||
// call to C function
|
||||
jal ra, irq
|
||||
|
||||
/* restore registers */
|
||||
|
||||
#ifdef ENABLE_QREGS
|
||||
|
||||
// new irq_regs address returned from C code in a0
|
||||
addi x1, a0, 0
|
||||
|
||||
lw x2, 0*4(x1)
|
||||
picorv32_setq_insn(q0, x2)
|
||||
|
||||
lw x2, 1*4(x1)
|
||||
picorv32_setq_insn(q1, x2)
|
||||
|
||||
lw x2, 2*4(x1)
|
||||
picorv32_setq_insn(q2, x2)
|
||||
|
||||
#ifdef ENABLE_FASTIRQ
|
||||
lw x5, 5*4(x1)
|
||||
lw x6, 6*4(x1)
|
||||
lw x7, 7*4(x1)
|
||||
lw x10, 10*4(x1)
|
||||
lw x11, 11*4(x1)
|
||||
lw x12, 12*4(x1)
|
||||
lw x13, 13*4(x1)
|
||||
lw x14, 14*4(x1)
|
||||
lw x15, 15*4(x1)
|
||||
lw x16, 16*4(x1)
|
||||
lw x17, 17*4(x1)
|
||||
lw x28, 28*4(x1)
|
||||
lw x29, 29*4(x1)
|
||||
lw x30, 30*4(x1)
|
||||
lw x31, 31*4(x1)
|
||||
#else
|
||||
lw x3, 3*4(x1)
|
||||
lw x4, 4*4(x1)
|
||||
lw x5, 5*4(x1)
|
||||
lw x6, 6*4(x1)
|
||||
lw x7, 7*4(x1)
|
||||
lw x8, 8*4(x1)
|
||||
lw x9, 9*4(x1)
|
||||
lw x10, 10*4(x1)
|
||||
lw x11, 11*4(x1)
|
||||
lw x12, 12*4(x1)
|
||||
lw x13, 13*4(x1)
|
||||
lw x14, 14*4(x1)
|
||||
lw x15, 15*4(x1)
|
||||
lw x16, 16*4(x1)
|
||||
lw x17, 17*4(x1)
|
||||
lw x18, 18*4(x1)
|
||||
lw x19, 19*4(x1)
|
||||
lw x20, 20*4(x1)
|
||||
lw x21, 21*4(x1)
|
||||
lw x22, 22*4(x1)
|
||||
lw x23, 23*4(x1)
|
||||
lw x24, 24*4(x1)
|
||||
lw x25, 25*4(x1)
|
||||
lw x26, 26*4(x1)
|
||||
lw x27, 27*4(x1)
|
||||
lw x28, 28*4(x1)
|
||||
lw x29, 29*4(x1)
|
||||
lw x30, 30*4(x1)
|
||||
lw x31, 31*4(x1)
|
||||
#endif
|
||||
|
||||
picorv32_getq_insn(x1, q1)
|
||||
picorv32_getq_insn(x2, q2)
|
||||
|
||||
#else // ENABLE_QREGS
|
||||
|
||||
// new irq_regs address returned from C code in a0
|
||||
addi a1, zero, 0x200
|
||||
beq a0, a1, 1f
|
||||
ebreak
|
||||
1:
|
||||
|
||||
#ifdef ENABLE_FASTIRQ
|
||||
lw gp, 0*4+0x200(zero)
|
||||
lw x1, 1*4+0x200(zero)
|
||||
lw x2, 2*4+0x200(zero)
|
||||
lw x5, 5*4+0x200(zero)
|
||||
lw x6, 6*4+0x200(zero)
|
||||
lw x7, 7*4+0x200(zero)
|
||||
lw x10, 10*4+0x200(zero)
|
||||
lw x11, 11*4+0x200(zero)
|
||||
lw x12, 12*4+0x200(zero)
|
||||
lw x13, 13*4+0x200(zero)
|
||||
lw x14, 14*4+0x200(zero)
|
||||
lw x15, 15*4+0x200(zero)
|
||||
lw x16, 16*4+0x200(zero)
|
||||
lw x17, 17*4+0x200(zero)
|
||||
lw x28, 28*4+0x200(zero)
|
||||
lw x29, 29*4+0x200(zero)
|
||||
lw x30, 30*4+0x200(zero)
|
||||
lw x31, 31*4+0x200(zero)
|
||||
#else
|
||||
lw gp, 0*4+0x200(zero)
|
||||
lw x1, 1*4+0x200(zero)
|
||||
lw x2, 2*4+0x200(zero)
|
||||
// do not restore x3 (gp)
|
||||
lw x4, 4*4+0x200(zero)
|
||||
lw x5, 5*4+0x200(zero)
|
||||
lw x6, 6*4+0x200(zero)
|
||||
lw x7, 7*4+0x200(zero)
|
||||
lw x8, 8*4+0x200(zero)
|
||||
lw x9, 9*4+0x200(zero)
|
||||
lw x10, 10*4+0x200(zero)
|
||||
lw x11, 11*4+0x200(zero)
|
||||
lw x12, 12*4+0x200(zero)
|
||||
lw x13, 13*4+0x200(zero)
|
||||
lw x14, 14*4+0x200(zero)
|
||||
lw x15, 15*4+0x200(zero)
|
||||
lw x16, 16*4+0x200(zero)
|
||||
lw x17, 17*4+0x200(zero)
|
||||
lw x18, 18*4+0x200(zero)
|
||||
lw x19, 19*4+0x200(zero)
|
||||
lw x20, 20*4+0x200(zero)
|
||||
lw x21, 21*4+0x200(zero)
|
||||
lw x22, 22*4+0x200(zero)
|
||||
lw x23, 23*4+0x200(zero)
|
||||
lw x24, 24*4+0x200(zero)
|
||||
lw x25, 25*4+0x200(zero)
|
||||
lw x26, 26*4+0x200(zero)
|
||||
lw x27, 27*4+0x200(zero)
|
||||
lw x28, 28*4+0x200(zero)
|
||||
lw x29, 29*4+0x200(zero)
|
||||
lw x30, 30*4+0x200(zero)
|
||||
lw x31, 31*4+0x200(zero)
|
||||
#endif
|
||||
|
||||
#endif // ENABLE_QREGS
|
||||
|
||||
picorv32_retirq_insn()
|
||||
|
||||
#ifndef ENABLE_QREGS
|
||||
.balign 0x200
|
||||
#endif
|
||||
irq_regs:
|
||||
// registers are saved to this memory region during interrupt handling
|
||||
// the program counter is saved as register 0
|
||||
.fill 32,4
|
||||
|
||||
// stack for the interrupt handler
|
||||
.fill 128,4
|
||||
irq_stack:
|
||||
|
||||
|
||||
/* Main program
|
||||
**********************************/
|
||||
|
||||
start:
|
||||
/* zero-initialize all registers */
|
||||
|
||||
addi x1, zero, 0
|
||||
addi x2, zero, 0
|
||||
addi x3, zero, 0
|
||||
addi x4, zero, 0
|
||||
addi x5, zero, 0
|
||||
addi x6, zero, 0
|
||||
addi x7, zero, 0
|
||||
addi x8, zero, 0
|
||||
addi x9, zero, 0
|
||||
addi x10, zero, 0
|
||||
addi x11, zero, 0
|
||||
addi x12, zero, 0
|
||||
addi x13, zero, 0
|
||||
addi x14, zero, 0
|
||||
addi x15, zero, 0
|
||||
addi x16, zero, 0
|
||||
addi x17, zero, 0
|
||||
addi x18, zero, 0
|
||||
addi x19, zero, 0
|
||||
addi x20, zero, 0
|
||||
addi x21, zero, 0
|
||||
addi x22, zero, 0
|
||||
addi x23, zero, 0
|
||||
addi x24, zero, 0
|
||||
addi x25, zero, 0
|
||||
addi x26, zero, 0
|
||||
addi x27, zero, 0
|
||||
addi x28, zero, 0
|
||||
addi x29, zero, 0
|
||||
addi x30, zero, 0
|
||||
addi x31, zero, 0
|
||||
|
||||
/* running tests from riscv-tests */
|
||||
|
||||
#ifdef ENABLE_RVTST
|
||||
# define TEST(n) \
|
||||
.global n; \
|
||||
addi x1, zero, 1000; \
|
||||
picorv32_timer_insn(zero, x1); \
|
||||
jal zero,n; \
|
||||
.global n ## _ret; \
|
||||
n ## _ret:
|
||||
#else
|
||||
# define TEST(n) \
|
||||
.global n ## _ret; \
|
||||
n ## _ret:
|
||||
#endif
|
||||
|
||||
TEST(lui)
|
||||
TEST(auipc)
|
||||
TEST(j)
|
||||
TEST(jal)
|
||||
TEST(jalr)
|
||||
|
||||
TEST(beq)
|
||||
TEST(bne)
|
||||
TEST(blt)
|
||||
TEST(bge)
|
||||
TEST(bltu)
|
||||
TEST(bgeu)
|
||||
|
||||
TEST(lb)
|
||||
TEST(lh)
|
||||
TEST(lw)
|
||||
TEST(lbu)
|
||||
TEST(lhu)
|
||||
|
||||
TEST(sb)
|
||||
TEST(sh)
|
||||
TEST(sw)
|
||||
|
||||
TEST(addi)
|
||||
TEST(slti) // also tests sltiu
|
||||
TEST(xori)
|
||||
TEST(ori)
|
||||
TEST(andi)
|
||||
TEST(slli)
|
||||
TEST(srli)
|
||||
TEST(srai)
|
||||
|
||||
TEST(add)
|
||||
TEST(sub)
|
||||
TEST(sll)
|
||||
TEST(slt) // what is with sltu ?
|
||||
TEST(xor)
|
||||
TEST(srl)
|
||||
TEST(sra)
|
||||
TEST(or)
|
||||
TEST(and)
|
||||
|
||||
// TEST(mulh)
|
||||
// TEST(mulhsu)
|
||||
// TEST(mulhu)
|
||||
// TEST(mul)
|
||||
|
||||
// TEST(div)
|
||||
// TEST(divu)
|
||||
// TEST(rem)
|
||||
// TEST(remu)
|
||||
|
||||
TEST(simple)
|
||||
|
||||
/* set stack pointer */
|
||||
lui sp,(64*1024)>>12
|
||||
|
||||
/* set gp and tp */
|
||||
lui gp, %hi(0xdeadbeef)
|
||||
addi gp, gp, %lo(0xdeadbeef)
|
||||
addi tp, gp, 0
|
||||
|
||||
#ifdef ENABLE_SIEVE
|
||||
/* call sieve C code */
|
||||
jal ra,sieve
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_MULTST
|
||||
/* call multest C code */
|
||||
jal ra,multest
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_STATS
|
||||
/* call stats C code */
|
||||
jal ra,stats
|
||||
#endif
|
||||
|
||||
/* print "DONE\n" */
|
||||
lui a0,0x10000000>>12
|
||||
addi a1,zero,'D'
|
||||
addi a2,zero,'O'
|
||||
addi a3,zero,'N'
|
||||
addi a4,zero,'E'
|
||||
addi a5,zero,'\n'
|
||||
sw a1,0(a0)
|
||||
sw a2,0(a0)
|
||||
sw a3,0(a0)
|
||||
sw a4,0(a0)
|
||||
sw a5,0(a0)
|
||||
|
||||
li a0, 0x20000000
|
||||
li a1, 123456789
|
||||
sw a1,0(a0)
|
||||
|
||||
/* trap */
|
||||
ebreak
|
||||
|
||||
|
||||
/* Hard mul functions for multest.c
|
||||
**********************************/
|
||||
|
||||
//hard_mul:
|
||||
// mul a0, a0, a1
|
||||
// ret
|
||||
//
|
||||
//hard_mulh:
|
||||
// mulh a0, a0, a1
|
||||
// ret
|
||||
//
|
||||
//hard_mulhsu:
|
||||
// mulhsu a0, a0, a1
|
||||
// ret
|
||||
//
|
||||
//hard_mulhu:
|
||||
// mulhu a0, a0, a1
|
||||
// ret
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
// This is free and unencumbered software released into the public domain.
|
||||
//
|
||||
// Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
// distribute this software, either in source code form or as a compiled
|
||||
// binary, for any purpose, commercial or non-commercial, and by any
|
||||
// means.
|
||||
|
||||
#include "firmware.h"
|
||||
|
||||
static void stats_print_dec(unsigned int val, int digits, bool zero_pad)
|
||||
{
|
||||
char buffer[32];
|
||||
char *p = buffer;
|
||||
while (val || digits > 0) {
|
||||
if (val)
|
||||
*(p++) = '0' + val % 10;
|
||||
else
|
||||
*(p++) = zero_pad ? '0' : ' ';
|
||||
val = val / 10;
|
||||
digits--;
|
||||
}
|
||||
while (p != buffer) {
|
||||
if (p[-1] == ' ' && p[-2] == ' ') p[-1] = '.';
|
||||
print_chr(*(--p));
|
||||
}
|
||||
}
|
||||
|
||||
void stats(void)
|
||||
{
|
||||
unsigned int num_cycles, num_instr;
|
||||
__asm__ volatile ("rdcycle %0; rdinstret %1;" : "=r"(num_cycles), "=r"(num_instr));
|
||||
print_str("Cycle counter ........");
|
||||
stats_print_dec(num_cycles, 8, false);
|
||||
print_str("\nInstruction counter ..");
|
||||
stats_print_dec(num_instr, 8, false);
|
||||
print_str("\nCPI: ");
|
||||
stats_print_dec((num_cycles / num_instr), 0, false);
|
||||
print_str(".");
|
||||
stats_print_dec(((100 * num_cycles) / num_instr) % 100, 2, true);
|
||||
print_str("\n");
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -1,24 +0,0 @@
|
||||
Copyright (c) 2012-2015, The Regents of the University of California (Regents).
|
||||
All Rights Reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the Regents nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
|
||||
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
|
||||
OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
|
||||
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
|
||||
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
|
||||
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
|
||||
@@ -1 +0,0 @@
|
||||
Tests from https://github.com/riscv/riscv-tests/tree/master/isa/rv32ui
|
||||
@@ -1,85 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# add.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test add instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 );
|
||||
|
||||
TEST_RR_OP( 5, add, 0xffff8000, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 6, add, 0x80000000, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 7, add, 0x7fff8000, 0x80000000, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP( 8, add, 0x00007fff, 0x00000000, 0x00007fff );
|
||||
TEST_RR_OP( 9, add, 0x7fffffff, 0x7fffffff, 0x00000000 );
|
||||
TEST_RR_OP( 10, add, 0x80007ffe, 0x7fffffff, 0x00007fff );
|
||||
|
||||
TEST_RR_OP( 11, add, 0x80007fff, 0x80000000, 0x00007fff );
|
||||
TEST_RR_OP( 12, add, 0x7fff7fff, 0x7fffffff, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP( 13, add, 0xffffffff, 0x00000000, 0xffffffff );
|
||||
TEST_RR_OP( 14, add, 0x00000000, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP( 15, add, 0xfffffffe, 0xffffffff, 0xffffffff );
|
||||
|
||||
TEST_RR_OP( 16, add, 0x80000000, 0x00000001, 0x7fffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
|
||||
TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
|
||||
TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
|
||||
TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
|
||||
TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 35, add, 15, 15 );
|
||||
TEST_RR_ZEROSRC2( 36, add, 32, 32 );
|
||||
TEST_RR_ZEROSRC12( 37, add, 0 );
|
||||
TEST_RR_ZERODEST( 38, add, 16, 30 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,71 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# addi.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test addi instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 );
|
||||
TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 );
|
||||
TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 );
|
||||
|
||||
TEST_IMM_OP( 5, addi, 0xfffff800, 0x00000000, 0x800 );
|
||||
TEST_IMM_OP( 6, addi, 0x80000000, 0x80000000, 0x000 );
|
||||
TEST_IMM_OP( 7, addi, 0x7ffff800, 0x80000000, 0x800 );
|
||||
|
||||
TEST_IMM_OP( 8, addi, 0x000007ff, 0x00000000, 0x7ff );
|
||||
TEST_IMM_OP( 9, addi, 0x7fffffff, 0x7fffffff, 0x000 );
|
||||
TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff );
|
||||
|
||||
TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff );
|
||||
TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 );
|
||||
|
||||
TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff );
|
||||
TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 );
|
||||
TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff );
|
||||
|
||||
TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
|
||||
TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
|
||||
TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
|
||||
TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
|
||||
TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 );
|
||||
|
||||
TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
|
||||
TEST_IMM_ZERODEST( 25, addi, 33, 50 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,69 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# and.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test and instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Logical tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
|
||||
TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
|
||||
TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
|
||||
|
||||
TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
|
||||
TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
|
||||
TEST_RR_ZEROSRC12( 26, and, 0 );
|
||||
TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,55 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# andi.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test andi instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Logical tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
|
||||
TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
|
||||
TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
|
||||
TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
|
||||
TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
|
||||
TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
|
||||
TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
|
||||
TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
|
||||
|
||||
TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
|
||||
TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,39 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# auipc.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test auipc instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
TEST_CASE(2, a0, 10000, \
|
||||
.align 3; \
|
||||
lla a0, 1f + 10000; \
|
||||
jal a1, 1f; \
|
||||
1: sub a0, a0, a1; \
|
||||
)
|
||||
|
||||
TEST_CASE(3, a0, -10000, \
|
||||
.align 3; \
|
||||
lla a0, 1f - 10000; \
|
||||
jal a1, 1f; \
|
||||
1: sub a0, a0, a1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,73 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# beq.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test beq instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Branch tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
# Each test checks both forward and backward branches
|
||||
|
||||
TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
|
||||
TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
|
||||
TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
|
||||
|
||||
TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
|
||||
TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 21, x1, 3, \
|
||||
li x1, 1; \
|
||||
beq x0, x0, 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,76 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# bge.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test bge instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Branch tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
# Each test checks both forward and backward branches
|
||||
|
||||
TEST_BR2_OP_TAKEN( 2, bge, 0, 0 );
|
||||
TEST_BR2_OP_TAKEN( 3, bge, 1, 1 );
|
||||
TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
|
||||
TEST_BR2_OP_TAKEN( 5, bge, 1, 0 );
|
||||
TEST_BR2_OP_TAKEN( 6, bge, 1, -1 );
|
||||
TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
|
||||
|
||||
TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 24, x1, 3, \
|
||||
li x1, 1; \
|
||||
bge x1, x0, 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,76 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# bgeu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test bgeu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Branch tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
# Each test checks both forward and backward branches
|
||||
|
||||
TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
|
||||
TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
|
||||
TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
|
||||
TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
|
||||
TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
|
||||
TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
|
||||
|
||||
TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 );
|
||||
TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff );
|
||||
TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
|
||||
TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
|
||||
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 24, x1, 3, \
|
||||
li x1, 1; \
|
||||
bgeu x1, x0, 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,73 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# blt.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test blt instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Branch tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
# Each test checks both forward and backward branches
|
||||
|
||||
TEST_BR2_OP_TAKEN( 2, blt, 0, 1 );
|
||||
TEST_BR2_OP_TAKEN( 3, blt, -1, 1 );
|
||||
TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
|
||||
|
||||
TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 );
|
||||
TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
|
||||
TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
|
||||
TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 21, x1, 3, \
|
||||
li x1, 1; \
|
||||
blt x0, x1, 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,73 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# bltu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test bltu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Branch tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
# Each test checks both forward and backward branches
|
||||
|
||||
TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
|
||||
TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
|
||||
TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
|
||||
|
||||
TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
|
||||
TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
|
||||
TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
|
||||
TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
|
||||
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 21, x1, 3, \
|
||||
li x1, 1; \
|
||||
bltu x0, x1, 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,73 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# bne.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test bne instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Branch tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
# Each test checks both forward and backward branches
|
||||
|
||||
TEST_BR2_OP_TAKEN( 2, bne, 0, 1 );
|
||||
TEST_BR2_OP_TAKEN( 3, bne, 1, 0 );
|
||||
TEST_BR2_OP_TAKEN( 4, bne, -1, 1 );
|
||||
TEST_BR2_OP_TAKEN( 5, bne, 1, -1 );
|
||||
|
||||
TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 );
|
||||
TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 );
|
||||
TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
|
||||
|
||||
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
|
||||
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 21, x1, 3, \
|
||||
li x1, 1; \
|
||||
bne x1, x0, 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,41 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# div.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test div instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, div, 3, 20, 6 );
|
||||
TEST_RR_OP( 3, div, -3, -20, 6 );
|
||||
TEST_RR_OP( 4, div, -3, 20, -6 );
|
||||
TEST_RR_OP( 5, div, 3, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, div, -1<<31, -1<<31, 1 );
|
||||
TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 );
|
||||
|
||||
TEST_RR_OP( 8, div, -1, -1<<31, 0 );
|
||||
TEST_RR_OP( 9, div, -1, 1, 0 );
|
||||
TEST_RR_OP(10, div, -1, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,41 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# divu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test divu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, divu, 3, 20, 6 );
|
||||
TEST_RR_OP( 3, divu, 715827879, -20, 6 );
|
||||
TEST_RR_OP( 4, divu, 0, 20, -6 );
|
||||
TEST_RR_OP( 5, divu, 0, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
|
||||
TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
|
||||
|
||||
TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
|
||||
TEST_RR_OP( 9, divu, -1, 1, 0 );
|
||||
TEST_RR_OP(10, divu, -1, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,49 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# j.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test j instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test basic
|
||||
#-------------------------------------------------------------
|
||||
|
||||
li TESTNUM, 2;
|
||||
j test_2;
|
||||
j fail;
|
||||
test_2:
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 3, x1, 3, \
|
||||
li x1, 1; \
|
||||
j 1f; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,60 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# jal.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test jal instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test 2: Basic test
|
||||
#-------------------------------------------------------------
|
||||
|
||||
test_2:
|
||||
li TESTNUM, 2
|
||||
li ra, 0
|
||||
|
||||
linkaddr_2:
|
||||
jal target_2
|
||||
nop
|
||||
nop
|
||||
|
||||
j fail
|
||||
|
||||
target_2:
|
||||
la x2, linkaddr_2
|
||||
addi x2, x2, 4
|
||||
bne x2, ra, fail
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 3, x2, 3, \
|
||||
li x2, 1; \
|
||||
jal 1f; \
|
||||
addi x2, x2, 1; \
|
||||
addi x2, x2, 1; \
|
||||
addi x2, x2, 1; \
|
||||
addi x2, x2, 1; \
|
||||
1: addi x2, x2, 1; \
|
||||
addi x2, x2, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,88 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# jalr.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test jalr instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test 2: Basic test
|
||||
#-------------------------------------------------------------
|
||||
|
||||
test_2:
|
||||
li TESTNUM, 2
|
||||
li x31, 0
|
||||
la x2, target_2
|
||||
|
||||
linkaddr_2:
|
||||
jalr x19, x2, 0
|
||||
nop
|
||||
nop
|
||||
|
||||
j fail
|
||||
|
||||
target_2:
|
||||
la x1, linkaddr_2
|
||||
addi x1, x1, 4
|
||||
bne x1, x19, fail
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test 3: Check r0 target and that r31 is not modified
|
||||
#-------------------------------------------------------------
|
||||
|
||||
test_3:
|
||||
li TESTNUM, 3
|
||||
li x31, 0
|
||||
la x3, target_3
|
||||
|
||||
linkaddr_3:
|
||||
jalr x0, x3, 0
|
||||
nop
|
||||
|
||||
j fail
|
||||
|
||||
target_3:
|
||||
bne x31, x0, fail
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
|
||||
TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
|
||||
TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test delay slot instructions not executed nor bypassed
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 7, x1, 4, \
|
||||
li x1, 1; \
|
||||
la x2, 1f;
|
||||
jalr x19, x2, -4; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
1: addi x1, x1, 1; \
|
||||
addi x1, x1, 1; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,92 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# lb.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test lb instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_OP( 2, lb, 0xffffffff, 0, tdat );
|
||||
TEST_LD_OP( 3, lb, 0x00000000, 1, tdat );
|
||||
TEST_LD_OP( 4, lb, 0xfffffff0, 2, tdat );
|
||||
TEST_LD_OP( 5, lb, 0x0000000f, 3, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_LD_OP( 6, lb, 0xffffffff, -3, tdat4 );
|
||||
TEST_LD_OP( 7, lb, 0x00000000, -2, tdat4 );
|
||||
TEST_LD_OP( 8, lb, 0xfffffff0, -1, tdat4 );
|
||||
TEST_LD_OP( 9, lb, 0x0000000f, 0, tdat4 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0xffffffff, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -32; \
|
||||
lb x3, 32(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0x00000000, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -6; \
|
||||
lb x3, 7(x1); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffff0, 1, tdat2 );
|
||||
TEST_LD_DEST_BYPASS( 13, 1, lb, 0x0000000f, 1, tdat3 );
|
||||
TEST_LD_DEST_BYPASS( 14, 2, lb, 0x00000000, 1, tdat1 );
|
||||
|
||||
TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffff0, 1, tdat2 );
|
||||
TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x0000000f, 1, tdat3 );
|
||||
TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x00000000, 1, tdat1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test write-after-write hazard
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 18, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lb x2, 0(x3); \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_CASE( 19, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lb x2, 0(x3); \
|
||||
nop; \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .byte 0xff
|
||||
tdat2: .byte 0x00
|
||||
tdat3: .byte 0xf0
|
||||
tdat4: .byte 0x0f
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,92 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# lbu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test lbu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_OP( 2, lbu, 0x000000ff, 0, tdat );
|
||||
TEST_LD_OP( 3, lbu, 0x00000000, 1, tdat );
|
||||
TEST_LD_OP( 4, lbu, 0x000000f0, 2, tdat );
|
||||
TEST_LD_OP( 5, lbu, 0x0000000f, 3, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_LD_OP( 6, lbu, 0x000000ff, -3, tdat4 );
|
||||
TEST_LD_OP( 7, lbu, 0x00000000, -2, tdat4 );
|
||||
TEST_LD_OP( 8, lbu, 0x000000f0, -1, tdat4 );
|
||||
TEST_LD_OP( 9, lbu, 0x0000000f, 0, tdat4 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0x000000ff, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -32; \
|
||||
lbu x3, 32(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0x00000000, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -6; \
|
||||
lbu x3, 7(x1); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x000000f0, 1, tdat2 );
|
||||
TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x0000000f, 1, tdat3 );
|
||||
TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x00000000, 1, tdat1 );
|
||||
|
||||
TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x000000f0, 1, tdat2 );
|
||||
TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x0000000f, 1, tdat3 );
|
||||
TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x00000000, 1, tdat1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test write-after-write hazard
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 18, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lbu x2, 0(x3); \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_CASE( 19, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lbu x2, 0(x3); \
|
||||
nop; \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .byte 0xff
|
||||
tdat2: .byte 0x00
|
||||
tdat3: .byte 0xf0
|
||||
tdat4: .byte 0x0f
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,92 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# lh.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test lh instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_OP( 2, lh, 0x000000ff, 0, tdat );
|
||||
TEST_LD_OP( 3, lh, 0xffffff00, 2, tdat );
|
||||
TEST_LD_OP( 4, lh, 0x00000ff0, 4, tdat );
|
||||
TEST_LD_OP( 5, lh, 0xfffff00f, 6, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_LD_OP( 6, lh, 0x000000ff, -6, tdat4 );
|
||||
TEST_LD_OP( 7, lh, 0xffffff00, -4, tdat4 );
|
||||
TEST_LD_OP( 8, lh, 0x00000ff0, -2, tdat4 );
|
||||
TEST_LD_OP( 9, lh, 0xfffff00f, 0, tdat4 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0x000000ff, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -32; \
|
||||
lh x3, 32(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0xffffff00, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -5; \
|
||||
lh x3, 7(x1); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_DEST_BYPASS( 12, 0, lh, 0x00000ff0, 2, tdat2 );
|
||||
TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffff00f, 2, tdat3 );
|
||||
TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffff00, 2, tdat1 );
|
||||
|
||||
TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x00000ff0, 2, tdat2 );
|
||||
TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffff00f, 2, tdat3 );
|
||||
TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffff00, 2, tdat1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test write-after-write hazard
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 18, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lh x2, 0(x3); \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_CASE( 19, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lh x2, 0(x3); \
|
||||
nop; \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .half 0x00ff
|
||||
tdat2: .half 0xff00
|
||||
tdat3: .half 0x0ff0
|
||||
tdat4: .half 0xf00f
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,92 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# lhu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test lhu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_OP( 2, lhu, 0x000000ff, 0, tdat );
|
||||
TEST_LD_OP( 3, lhu, 0x0000ff00, 2, tdat );
|
||||
TEST_LD_OP( 4, lhu, 0x00000ff0, 4, tdat );
|
||||
TEST_LD_OP( 5, lhu, 0x0000f00f, 6, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_LD_OP( 6, lhu, 0x000000ff, -6, tdat4 );
|
||||
TEST_LD_OP( 7, lhu, 0x0000ff00, -4, tdat4 );
|
||||
TEST_LD_OP( 8, lhu, 0x00000ff0, -2, tdat4 );
|
||||
TEST_LD_OP( 9, lhu, 0x0000f00f, 0, tdat4 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0x000000ff, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -32; \
|
||||
lhu x3, 32(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0x0000ff00, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -5; \
|
||||
lhu x3, 7(x1); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x00000ff0, 2, tdat2 );
|
||||
TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x0000f00f, 2, tdat3 );
|
||||
TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x0000ff00, 2, tdat1 );
|
||||
|
||||
TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x00000ff0, 2, tdat2 );
|
||||
TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x0000f00f, 2, tdat3 );
|
||||
TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x0000ff00, 2, tdat1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test write-after-write hazard
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 18, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lhu x2, 0(x3); \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_CASE( 19, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lhu x2, 0(x3); \
|
||||
nop; \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .half 0x00ff
|
||||
tdat2: .half 0xff00
|
||||
tdat3: .half 0x0ff0
|
||||
tdat4: .half 0xf00f
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,36 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# lui.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test lui instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 2, x1, 0x00000000, lui x1, 0x00000 );
|
||||
TEST_CASE( 3, x1, 0xfffff800, lui x1, 0xfffff;sra x1,x1,1);
|
||||
TEST_CASE( 4, x1, 0x000007ff, lui x1, 0x7ffff;sra x1,x1,20);
|
||||
TEST_CASE( 5, x1, 0xfffff800, lui x1, 0x80000;sra x1,x1,20);
|
||||
|
||||
TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,92 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# lw.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test lw instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_OP( 2, lw, 0x00ff00ff, 0, tdat );
|
||||
TEST_LD_OP( 3, lw, 0xff00ff00, 4, tdat );
|
||||
TEST_LD_OP( 4, lw, 0x0ff00ff0, 8, tdat );
|
||||
TEST_LD_OP( 5, lw, 0xf00ff00f, 12, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_LD_OP( 6, lw, 0x00ff00ff, -12, tdat4 );
|
||||
TEST_LD_OP( 7, lw, 0xff00ff00, -8, tdat4 );
|
||||
TEST_LD_OP( 8, lw, 0x0ff00ff0, -4, tdat4 );
|
||||
TEST_LD_OP( 9, lw, 0xf00ff00f, 0, tdat4 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0x00ff00ff, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -32; \
|
||||
lw x3, 32(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0xff00ff00, \
|
||||
la x1, tdat; \
|
||||
addi x1, x1, -3; \
|
||||
lw x3, 7(x1); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_LD_DEST_BYPASS( 12, 0, lw, 0x0ff00ff0, 4, tdat2 );
|
||||
TEST_LD_DEST_BYPASS( 13, 1, lw, 0xf00ff00f, 4, tdat3 );
|
||||
TEST_LD_DEST_BYPASS( 14, 2, lw, 0xff00ff00, 4, tdat1 );
|
||||
|
||||
TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x0ff00ff0, 4, tdat2 );
|
||||
TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xf00ff00f, 4, tdat3 );
|
||||
TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xff00ff00, 4, tdat1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Test write-after-write hazard
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_CASE( 18, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lw x2, 0(x3); \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_CASE( 19, x2, 2, \
|
||||
la x3, tdat; \
|
||||
lw x2, 0(x3); \
|
||||
nop; \
|
||||
li x2, 2; \
|
||||
)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .word 0x00ff00ff
|
||||
tdat2: .word 0xff00ff00
|
||||
tdat3: .word 0x0ff00ff0
|
||||
tdat4: .word 0xf00ff00f
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,84 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# mul.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test mul instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
|
||||
TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
|
||||
|
||||
TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
|
||||
|
||||
TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
|
||||
TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
|
||||
|
||||
TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
|
||||
|
||||
TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
|
||||
TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
|
||||
TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
|
||||
TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
|
||||
TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
|
||||
TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
|
||||
TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
|
||||
TEST_RR_ZEROSRC12( 28, mul, 0 );
|
||||
TEST_RR_ZERODEST( 29, mul, 33, 34 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,81 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# mulh.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test mulh instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
|
||||
|
||||
TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
|
||||
|
||||
TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
|
||||
TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
|
||||
|
||||
TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
|
||||
|
||||
TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
|
||||
TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
|
||||
TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
|
||||
TEST_RR_ZEROSRC12( 28, mulh, 0 );
|
||||
TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,83 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# mulhsu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test mulhsu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
|
||||
|
||||
TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
|
||||
TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
|
||||
|
||||
TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
|
||||
|
||||
TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
|
||||
TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
|
||||
TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
|
||||
TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
|
||||
TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
|
||||
|
||||
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,82 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# mulhu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test mulhu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
|
||||
|
||||
TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
|
||||
TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
|
||||
|
||||
TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
|
||||
|
||||
TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
|
||||
TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
|
||||
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
|
||||
TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
|
||||
TEST_RR_ZEROSRC12( 28, mulhu, 0 );
|
||||
TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
|
||||
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,69 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# or.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test or instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Logical tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
|
||||
TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
|
||||
TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
|
||||
TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
|
||||
TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
|
||||
|
||||
TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
|
||||
TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
|
||||
TEST_RR_ZEROSRC12( 26, or, 0 );
|
||||
TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,55 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# ori.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test ori instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Logical tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, ori, 0xffffff0f, 0xff00ff00, 0xf0f );
|
||||
TEST_IMM_OP( 3, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
|
||||
TEST_IMM_OP( 4, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
|
||||
TEST_IMM_OP( 5, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
|
||||
TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
|
||||
TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
|
||||
TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffff, 0x00ff00ff, 0xf0f );
|
||||
TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
|
||||
|
||||
TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
|
||||
TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,41 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# rem.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test rem instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, rem, 2, 20, 6 );
|
||||
TEST_RR_OP( 3, rem, -2, -20, 6 );
|
||||
TEST_RR_OP( 4, rem, 2, 20, -6 );
|
||||
TEST_RR_OP( 5, rem, -2, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, rem, 0, -1<<31, 1 );
|
||||
TEST_RR_OP( 7, rem, 0, -1<<31, -1 );
|
||||
|
||||
TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 );
|
||||
TEST_RR_OP( 9, rem, 1, 1, 0 );
|
||||
TEST_RR_OP(10, rem, 0, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,41 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# remu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test remu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, remu, 2, 20, 6 );
|
||||
TEST_RR_OP( 3, remu, 2, -20, 6 );
|
||||
TEST_RR_OP( 4, remu, 20, 20, -6 );
|
||||
TEST_RR_OP( 5, remu, -20, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, remu, 0, -1<<31, 1 );
|
||||
TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 );
|
||||
|
||||
TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 );
|
||||
TEST_RR_OP( 9, remu, 1, 1, 0 );
|
||||
TEST_RR_OP(10, remu, 0, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
@@ -1,64 +0,0 @@
|
||||
#ifndef _ENV_PICORV32_TEST_H
|
||||
#define _ENV_PICORV32_TEST_H
|
||||
|
||||
#ifndef TEST_FUNC_NAME
|
||||
# define TEST_FUNC_NAME mytest
|
||||
# define TEST_FUNC_TXT "mytest"
|
||||
# define TEST_FUNC_RET mytest_ret
|
||||
#endif
|
||||
|
||||
#define RVTEST_RV32U
|
||||
#define TESTNUM x28
|
||||
|
||||
#define RVTEST_CODE_BEGIN \
|
||||
.text; \
|
||||
.global TEST_FUNC_NAME; \
|
||||
.global TEST_FUNC_RET; \
|
||||
TEST_FUNC_NAME: \
|
||||
lui a0,%hi(.test_name); \
|
||||
addi a0,a0,%lo(.test_name); \
|
||||
lui a2,0x10000000>>12; \
|
||||
.prname_next: \
|
||||
lb a1,0(a0); \
|
||||
beq a1,zero,.prname_done; \
|
||||
sw a1,0(a2); \
|
||||
addi a0,a0,1; \
|
||||
jal zero,.prname_next; \
|
||||
.test_name: \
|
||||
.ascii TEST_FUNC_TXT; \
|
||||
.byte 0x00; \
|
||||
.balign 4, 0; \
|
||||
.prname_done: \
|
||||
addi a1,zero,'.'; \
|
||||
sw a1,0(a2); \
|
||||
sw a1,0(a2);
|
||||
|
||||
#define RVTEST_PASS \
|
||||
lui a0,0x10000000>>12; \
|
||||
addi a1,zero,'O'; \
|
||||
addi a2,zero,'K'; \
|
||||
addi a3,zero,'\n'; \
|
||||
sw a1,0(a0); \
|
||||
sw a2,0(a0); \
|
||||
sw a3,0(a0); \
|
||||
jal zero,TEST_FUNC_RET;
|
||||
|
||||
#define RVTEST_FAIL \
|
||||
lui a0,0x10000000>>12; \
|
||||
addi a1,zero,'E'; \
|
||||
addi a2,zero,'R'; \
|
||||
addi a3,zero,'O'; \
|
||||
addi a4,zero,'\n'; \
|
||||
sw a1,0(a0); \
|
||||
sw a2,0(a0); \
|
||||
sw a2,0(a0); \
|
||||
sw a3,0(a0); \
|
||||
sw a2,0(a0); \
|
||||
sw a4,0(a0); \
|
||||
ebreak;
|
||||
|
||||
#define RVTEST_CODE_END
|
||||
#define RVTEST_DATA_BEGIN .balign 4;
|
||||
#define RVTEST_DATA_END
|
||||
|
||||
#endif
|
||||
@@ -1,96 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# sb.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test sb instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_ST_OP( 2, lb, sb, 0xffffffaa, 0, tdat );
|
||||
TEST_ST_OP( 3, lb, sb, 0x00000000, 1, tdat );
|
||||
TEST_ST_OP( 4, lh, sb, 0xffffefa0, 2, tdat );
|
||||
TEST_ST_OP( 5, lb, sb, 0x0000000a, 3, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_ST_OP( 6, lb, sb, 0xffffffaa, -3, tdat8 );
|
||||
TEST_ST_OP( 7, lb, sb, 0x00000000, -2, tdat8 );
|
||||
TEST_ST_OP( 8, lb, sb, 0xffffffa0, -1, tdat8 );
|
||||
TEST_ST_OP( 9, lb, sb, 0x0000000a, 0, tdat8 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0x78, \
|
||||
la x1, tdat9; \
|
||||
li x2, 0x12345678; \
|
||||
addi x4, x1, -32; \
|
||||
sb x2, 32(x4); \
|
||||
lb x3, 0(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0xffffff98, \
|
||||
la x1, tdat9; \
|
||||
li x2, 0x00003098; \
|
||||
addi x1, x1, -6; \
|
||||
sb x2, 7(x1); \
|
||||
la x4, tdat10; \
|
||||
lb x3, 0(x4); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffdd, 0, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffcd, 1, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffcc, 2, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffbc, 3, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffbb, 4, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffab, 5, tdat );
|
||||
|
||||
TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
|
||||
|
||||
li a0, 0xef
|
||||
la a1, tdat
|
||||
sb a0, 3(a1)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .byte 0xef
|
||||
tdat2: .byte 0xef
|
||||
tdat3: .byte 0xef
|
||||
tdat4: .byte 0xef
|
||||
tdat5: .byte 0xef
|
||||
tdat6: .byte 0xef
|
||||
tdat7: .byte 0xef
|
||||
tdat8: .byte 0xef
|
||||
tdat9: .byte 0xef
|
||||
tdat10: .byte 0xef
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,96 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# sh.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test sh instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Basic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat );
|
||||
TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat );
|
||||
TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat );
|
||||
TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat );
|
||||
|
||||
# Test with negative offset
|
||||
|
||||
TEST_ST_OP( 6, lh, sh, 0x000000aa, -6, tdat8 );
|
||||
TEST_ST_OP( 7, lh, sh, 0xffffaa00, -4, tdat8 );
|
||||
TEST_ST_OP( 8, lh, sh, 0x00000aa0, -2, tdat8 );
|
||||
TEST_ST_OP( 9, lh, sh, 0xffffa00a, 0, tdat8 );
|
||||
|
||||
# Test with a negative base
|
||||
|
||||
TEST_CASE( 10, x3, 0x5678, \
|
||||
la x1, tdat9; \
|
||||
li x2, 0x12345678; \
|
||||
addi x4, x1, -32; \
|
||||
sh x2, 32(x4); \
|
||||
lh x3, 0(x1); \
|
||||
)
|
||||
|
||||
# Test with unaligned base
|
||||
|
||||
TEST_CASE( 11, x3, 0x3098, \
|
||||
la x1, tdat9; \
|
||||
li x2, 0x00003098; \
|
||||
addi x1, x1, -5; \
|
||||
sh x2, 7(x1); \
|
||||
la x4, tdat10; \
|
||||
lh x3, 0(x4); \
|
||||
)
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffccdd, 0, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffbccd, 2, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffbbcc, 4, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffabbc, 6, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffaabb, 8, tdat );
|
||||
TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffdaab, 10, tdat );
|
||||
|
||||
TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
|
||||
TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
|
||||
|
||||
li a0, 0xbeef
|
||||
la a1, tdat
|
||||
sh a0, 6(a1)
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
tdat:
|
||||
tdat1: .half 0xbeef
|
||||
tdat2: .half 0xbeef
|
||||
tdat3: .half 0xbeef
|
||||
tdat4: .half 0xbeef
|
||||
tdat5: .half 0xbeef
|
||||
tdat6: .half 0xbeef
|
||||
tdat7: .half 0xbeef
|
||||
tdat8: .half 0xbeef
|
||||
tdat9: .half 0xbeef
|
||||
tdat10: .half 0xbeef
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,27 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# simple.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# This is the most basic self checking test. If your simulator does not
|
||||
# pass thiss then there is little chance that it will pass any of the
|
||||
# more complicated self checking tests.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_PASS
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,90 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# sll.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test sll instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, sll, 0x00000001, 0x00000001, 0 );
|
||||
TEST_RR_OP( 3, sll, 0x00000002, 0x00000001, 1 );
|
||||
TEST_RR_OP( 4, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_OP( 5, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_OP( 6, sll, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_RR_OP( 7, sll, 0xffffffff, 0xffffffff, 0 );
|
||||
TEST_RR_OP( 8, sll, 0xfffffffe, 0xffffffff, 1 );
|
||||
TEST_RR_OP( 9, sll, 0xffffff80, 0xffffffff, 7 );
|
||||
TEST_RR_OP( 10, sll, 0xffffc000, 0xffffffff, 14 );
|
||||
TEST_RR_OP( 11, sll, 0x80000000, 0xffffffff, 31 );
|
||||
|
||||
TEST_RR_OP( 12, sll, 0x21212121, 0x21212121, 0 );
|
||||
TEST_RR_OP( 13, sll, 0x42424242, 0x21212121, 1 );
|
||||
TEST_RR_OP( 14, sll, 0x90909080, 0x21212121, 7 );
|
||||
TEST_RR_OP( 15, sll, 0x48484000, 0x21212121, 14 );
|
||||
TEST_RR_OP( 16, sll, 0x80000000, 0x21212121, 31 );
|
||||
|
||||
# Verify that shifts only use bottom five bits
|
||||
|
||||
TEST_RR_OP( 17, sll, 0x21212121, 0x21212121, 0xffffffe0 );
|
||||
TEST_RR_OP( 18, sll, 0x42424242, 0x21212121, 0xffffffe1 );
|
||||
TEST_RR_OP( 19, sll, 0x90909080, 0x21212121, 0xffffffe7 );
|
||||
TEST_RR_OP( 20, sll, 0x48484000, 0x21212121, 0xffffffee );
|
||||
TEST_RR_OP( 21, sll, 0x00000000, 0x21212120, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 25, 0, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_DEST_BYPASS( 26, 1, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_DEST_BYPASS( 27, 2, sll, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x80000000, 0x00000001, 31 );
|
||||
TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x80000000, 0x00000001, 31 );
|
||||
TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x00000080, 0x00000001, 7 );
|
||||
TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x00004000, 0x00000001, 14 );
|
||||
TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
|
||||
TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
|
||||
TEST_RR_ZEROSRC12( 42, sll, 0 );
|
||||
TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,68 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# slli.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test slli instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, slli, 0x00000001, 0x00000001, 0 );
|
||||
TEST_IMM_OP( 3, slli, 0x00000002, 0x00000001, 1 );
|
||||
TEST_IMM_OP( 4, slli, 0x00000080, 0x00000001, 7 );
|
||||
TEST_IMM_OP( 5, slli, 0x00004000, 0x00000001, 14 );
|
||||
TEST_IMM_OP( 6, slli, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_IMM_OP( 7, slli, 0xffffffff, 0xffffffff, 0 );
|
||||
TEST_IMM_OP( 8, slli, 0xfffffffe, 0xffffffff, 1 );
|
||||
TEST_IMM_OP( 9, slli, 0xffffff80, 0xffffffff, 7 );
|
||||
TEST_IMM_OP( 10, slli, 0xffffc000, 0xffffffff, 14 );
|
||||
TEST_IMM_OP( 11, slli, 0x80000000, 0xffffffff, 31 );
|
||||
|
||||
TEST_IMM_OP( 12, slli, 0x21212121, 0x21212121, 0 );
|
||||
TEST_IMM_OP( 13, slli, 0x42424242, 0x21212121, 1 );
|
||||
TEST_IMM_OP( 14, slli, 0x90909080, 0x21212121, 7 );
|
||||
TEST_IMM_OP( 15, slli, 0x48484000, 0x21212121, 14 );
|
||||
TEST_IMM_OP( 16, slli, 0x80000000, 0x21212121, 31 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x00000080, 0x00000001, 7 );
|
||||
TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x00004000, 0x00000001, 14 );
|
||||
TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x00000080, 0x00000001, 7 );
|
||||
TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x00004000, 0x00000001, 14 );
|
||||
TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x80000000, 0x00000001, 31 );
|
||||
|
||||
TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
|
||||
TEST_IMM_ZERODEST( 25, slli, 33, 20 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,84 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# slt.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test slt instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, slt, 0, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, slt, 0, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, slt, 1, 0x00000003, 0x00000007 );
|
||||
TEST_RR_OP( 5, slt, 0, 0x00000007, 0x00000003 );
|
||||
|
||||
TEST_RR_OP( 6, slt, 0, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 7, slt, 1, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 8, slt, 1, 0x80000000, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP( 9, slt, 1, 0x00000000, 0x00007fff );
|
||||
TEST_RR_OP( 10, slt, 0, 0x7fffffff, 0x00000000 );
|
||||
TEST_RR_OP( 11, slt, 0, 0x7fffffff, 0x00007fff );
|
||||
|
||||
TEST_RR_OP( 12, slt, 1, 0x80000000, 0x00007fff );
|
||||
TEST_RR_OP( 13, slt, 0, 0x7fffffff, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP( 14, slt, 0, 0x00000000, 0xffffffff );
|
||||
TEST_RR_OP( 15, slt, 1, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP( 16, slt, 0, 0xffffffff, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
|
||||
TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
|
||||
TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
|
||||
TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
|
||||
TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
|
||||
TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
|
||||
TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
|
||||
TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
|
||||
TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
|
||||
TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
|
||||
TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 );
|
||||
TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
|
||||
TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 );
|
||||
TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
|
||||
TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
|
||||
TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
|
||||
TEST_RR_ZEROSRC12( 37, slt, 0 );
|
||||
TEST_RR_ZERODEST( 38, slt, 16, 30 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,70 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# slti.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test slti instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, slti, 0, 0x00000000, 0x000 );
|
||||
TEST_IMM_OP( 3, slti, 0, 0x00000001, 0x001 );
|
||||
TEST_IMM_OP( 4, slti, 1, 0x00000003, 0x007 );
|
||||
TEST_IMM_OP( 5, slti, 0, 0x00000007, 0x003 );
|
||||
|
||||
TEST_IMM_OP( 6, slti, 0, 0x00000000, 0x800 );
|
||||
TEST_IMM_OP( 7, slti, 1, 0x80000000, 0x000 );
|
||||
TEST_IMM_OP( 8, slti, 1, 0x80000000, 0x800 );
|
||||
|
||||
TEST_IMM_OP( 9, slti, 1, 0x00000000, 0x7ff );
|
||||
TEST_IMM_OP( 10, slti, 0, 0x7fffffff, 0x000 );
|
||||
TEST_IMM_OP( 11, slti, 0, 0x7fffffff, 0x7ff );
|
||||
|
||||
TEST_IMM_OP( 12, slti, 1, 0x80000000, 0x7ff );
|
||||
TEST_IMM_OP( 13, slti, 0, 0x7fffffff, 0x800 );
|
||||
|
||||
TEST_IMM_OP( 14, slti, 0, 0x00000000, 0xfff );
|
||||
TEST_IMM_OP( 15, slti, 1, 0xffffffff, 0x001 );
|
||||
TEST_IMM_OP( 16, slti, 0, 0xffffffff, 0xfff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
|
||||
TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
|
||||
TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
|
||||
TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 );
|
||||
TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
|
||||
|
||||
TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
|
||||
TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,90 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# sra.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test sra instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, sra, 0x80000000, 0x80000000, 0 );
|
||||
TEST_RR_OP( 3, sra, 0xc0000000, 0x80000000, 1 );
|
||||
TEST_RR_OP( 4, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_OP( 5, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_OP( 6, sra, 0xffffffff, 0x80000001, 31 );
|
||||
|
||||
TEST_RR_OP( 7, sra, 0x7fffffff, 0x7fffffff, 0 );
|
||||
TEST_RR_OP( 8, sra, 0x3fffffff, 0x7fffffff, 1 );
|
||||
TEST_RR_OP( 9, sra, 0x00ffffff, 0x7fffffff, 7 );
|
||||
TEST_RR_OP( 10, sra, 0x0001ffff, 0x7fffffff, 14 );
|
||||
TEST_RR_OP( 11, sra, 0x00000000, 0x7fffffff, 31 );
|
||||
|
||||
TEST_RR_OP( 12, sra, 0x81818181, 0x81818181, 0 );
|
||||
TEST_RR_OP( 13, sra, 0xc0c0c0c0, 0x81818181, 1 );
|
||||
TEST_RR_OP( 14, sra, 0xff030303, 0x81818181, 7 );
|
||||
TEST_RR_OP( 15, sra, 0xfffe0606, 0x81818181, 14 );
|
||||
TEST_RR_OP( 16, sra, 0xffffffff, 0x81818181, 31 );
|
||||
|
||||
# Verify that shifts only use bottom five bits
|
||||
|
||||
TEST_RR_OP( 17, sra, 0x81818181, 0x81818181, 0xffffffc0 );
|
||||
TEST_RR_OP( 18, sra, 0xc0c0c0c0, 0x81818181, 0xffffffc1 );
|
||||
TEST_RR_OP( 19, sra, 0xff030303, 0x81818181, 0xffffffc7 );
|
||||
TEST_RR_OP( 20, sra, 0xfffe0606, 0x81818181, 0xffffffce );
|
||||
TEST_RR_OP( 21, sra, 0xffffffff, 0x81818181, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 22, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 25, 0, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffff, 0x80000000, 31 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
|
||||
TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
|
||||
TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xff000000, 0x80000000, 7 );
|
||||
TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
|
||||
TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
|
||||
TEST_RR_ZEROSRC12( 42, sra, 0 );
|
||||
TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,68 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# srai.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test srai instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, srai, 0x00000000, 0x00000000, 0 );
|
||||
TEST_IMM_OP( 3, srai, 0xc0000000, 0x80000000, 1 );
|
||||
TEST_IMM_OP( 4, srai, 0xff000000, 0x80000000, 7 );
|
||||
TEST_IMM_OP( 5, srai, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_IMM_OP( 6, srai, 0xffffffff, 0x80000001, 31 );
|
||||
|
||||
TEST_IMM_OP( 7, srai, 0x7fffffff, 0x7fffffff, 0 );
|
||||
TEST_IMM_OP( 8, srai, 0x3fffffff, 0x7fffffff, 1 );
|
||||
TEST_IMM_OP( 9, srai, 0x00ffffff, 0x7fffffff, 7 );
|
||||
TEST_IMM_OP( 10, srai, 0x0001ffff, 0x7fffffff, 14 );
|
||||
TEST_IMM_OP( 11, srai, 0x00000000, 0x7fffffff, 31 );
|
||||
|
||||
TEST_IMM_OP( 12, srai, 0x81818181, 0x81818181, 0 );
|
||||
TEST_IMM_OP( 13, srai, 0xc0c0c0c0, 0x81818181, 1 );
|
||||
TEST_IMM_OP( 14, srai, 0xff030303, 0x81818181, 7 );
|
||||
TEST_IMM_OP( 15, srai, 0xfffe0606, 0x81818181, 14 );
|
||||
TEST_IMM_OP( 16, srai, 0xffffffff, 0x81818181, 31 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xff000000, 0x80000000, 7 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xff000000, 0x80000000, 7 );
|
||||
TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffff, 0x80000001, 31 );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xff000000, 0x80000000, 7 );
|
||||
TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffe0000, 0x80000000, 14 );
|
||||
TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffff, 0x80000001, 31 );
|
||||
|
||||
TEST_IMM_ZEROSRC1( 24, srai, 0, 31 );
|
||||
TEST_IMM_ZERODEST( 25, srai, 33, 20 );
|
||||
#
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,90 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# srl.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test srl instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, srl, 0xffff8000, 0xffff8000, 0 );
|
||||
TEST_RR_OP( 3, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_OP( 4, srl, 0x01ffff00, 0xffff8000, 7 );
|
||||
TEST_RR_OP( 5, srl, 0x0003fffe, 0xffff8000, 14 );
|
||||
TEST_RR_OP( 6, srl, 0x0001ffff, 0xffff8001, 15 );
|
||||
|
||||
TEST_RR_OP( 7, srl, 0xffffffff, 0xffffffff, 0 );
|
||||
TEST_RR_OP( 8, srl, 0x7fffffff, 0xffffffff, 1 );
|
||||
TEST_RR_OP( 9, srl, 0x01ffffff, 0xffffffff, 7 );
|
||||
TEST_RR_OP( 10, srl, 0x0003ffff, 0xffffffff, 14 );
|
||||
TEST_RR_OP( 11, srl, 0x00000001, 0xffffffff, 31 );
|
||||
|
||||
TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0 );
|
||||
TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1 );
|
||||
TEST_RR_OP( 14, srl, 0x00424242, 0x21212121, 7 );
|
||||
TEST_RR_OP( 15, srl, 0x00008484, 0x21212121, 14 );
|
||||
TEST_RR_OP( 16, srl, 0x00000000, 0x21212121, 31 );
|
||||
|
||||
# Verify that shifts only use bottom five bits
|
||||
|
||||
TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffe0 );
|
||||
TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffe1 );
|
||||
TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffe7 );
|
||||
TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffee );
|
||||
TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 22, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffe, 0xffff8000, 14 );
|
||||
TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
|
||||
TEST_RR_DEST_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
|
||||
TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
|
||||
TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
|
||||
TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
|
||||
TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
|
||||
TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
|
||||
TEST_RR_ZEROSRC12( 42, srl, 0 );
|
||||
TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,69 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# srli.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test srli instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_OP( 2, srli, 0xffff8000, 0xffff8000, 0 );
|
||||
TEST_IMM_OP( 3, srli, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_IMM_OP( 4, srli, 0x01ffff00, 0xffff8000, 7 );
|
||||
TEST_IMM_OP( 5, srli, 0x0003fffe, 0xffff8000, 14 );
|
||||
TEST_IMM_OP( 6, srli, 0x0001ffff, 0xffff8001, 15 );
|
||||
|
||||
TEST_IMM_OP( 7, srli, 0xffffffff, 0xffffffff, 0 );
|
||||
TEST_IMM_OP( 8, srli, 0x7fffffff, 0xffffffff, 1 );
|
||||
TEST_IMM_OP( 9, srli, 0x01ffffff, 0xffffffff, 7 );
|
||||
TEST_IMM_OP( 10, srli, 0x0003ffff, 0xffffffff, 14 );
|
||||
TEST_IMM_OP( 11, srli, 0x00000001, 0xffffffff, 31 );
|
||||
|
||||
TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0 );
|
||||
TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1 );
|
||||
TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7 );
|
||||
TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
|
||||
TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_SRC1_EQ_DEST( 21, srli, 0x7fffc000, 0xffff8000, 1 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
|
||||
TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
|
||||
TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
|
||||
TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
|
||||
TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
|
||||
|
||||
|
||||
TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
|
||||
TEST_IMM_ZERODEST( 29, srli, 33, 20 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Binary file not shown.
@@ -1,83 +0,0 @@
|
||||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# sub.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test sub instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, sub, 0x00000000, 0x00000000, 0x00000000 );
|
||||
TEST_RR_OP( 3, sub, 0x00000000, 0x00000001, 0x00000001 );
|
||||
TEST_RR_OP( 4, sub, 0xfffffffc, 0x00000003, 0x00000007 );
|
||||
|
||||
TEST_RR_OP( 5, sub, 0x00008000, 0x00000000, 0xffff8000 );
|
||||
TEST_RR_OP( 6, sub, 0x80000000, 0x80000000, 0x00000000 );
|
||||
TEST_RR_OP( 7, sub, 0x80008000, 0x80000000, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP( 8, sub, 0xffff8001, 0x00000000, 0x00007fff );
|
||||
TEST_RR_OP( 9, sub, 0x7fffffff, 0x7fffffff, 0x00000000 );
|
||||
TEST_RR_OP( 10, sub, 0x7fff8000, 0x7fffffff, 0x00007fff );
|
||||
|
||||
TEST_RR_OP( 11, sub, 0x7fff8001, 0x80000000, 0x00007fff );
|
||||
TEST_RR_OP( 12, sub, 0x80007fff, 0x7fffffff, 0xffff8000 );
|
||||
|
||||
TEST_RR_OP( 13, sub, 0x00000001, 0x00000000, 0xffffffff );
|
||||
TEST_RR_OP( 14, sub, 0xfffffffe, 0xffffffff, 0x00000001 );
|
||||
TEST_RR_OP( 15, sub, 0x00000000, 0xffffffff, 0xffffffff );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Source/Destination tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
|
||||
TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
|
||||
TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Bypassing tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
|
||||
TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
|
||||
TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
|
||||
|
||||
TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
|
||||
TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
|
||||
|
||||
TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
|
||||
TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
|
||||
|
||||
TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
|
||||
TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
|
||||
TEST_RR_ZEROSRC12( 36, sub, 0 );
|
||||
TEST_RR_ZERODEST( 37, sub, 16, 30 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user