servant: ice: rename service clock gen source

Make it more explicit that this clock generator is for the ICE FPGA
family.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>

servant.core

@@ -19,13 +19,15 @@ filesets:
     depend : [vlog_tb_utils]
 
   service:
-    files: [servant/ice40_pll.v, servant/service.v]
+    files:
+      - servant/ice40_pll.v
+      - servant/service_clock_gen.v
+      - servant/service.v
     file_type : verilogSource
     depend : ["fusesoc:utils:generators"]
 
   soc:
     files:
-      - servant/servant_clock_gen.v
       - servant/servant_timer.v
       - servant/servant_gpio.v
       - servant/servant_arbiter.v

servant/service.v

@@ -11,7 +11,7 @@ module service
    wire      wb_clk;
    wire      wb_rst;
 
-   servant_clock_gen #(.PLL (PLL))
+   service_clock_gen #(.PLL (PLL))
    clock_gen
      (.i_clk (i_clk),
       .o_clk (wb_clk),

servant/service_clock_gen.v

@@ -1,5 +1,5 @@
 `default_nettype none
-module servant_clock_gen
+module service_clock_gen
   (
    input wire  i_clk,
    output wire o_clk,