Separate state from o_bufreg_loop

rtl/serv_bufreg.v

@@ -5,7 +5,7 @@ module serv_bufreg
    input wire [4:2]   i_cnt,
    input wire [1:0]   i_cnt_r,
    input wire 	      i_en,
-   input wire 	      i_clr,
+   input wire 	      i_init,
    input wire 	      i_loop,
    input wire 	      i_rs1,
    input wire 	      i_rs1_en,
@@ -22,12 +22,13 @@ module serv_bufreg
    assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en)} + c_r;
 
    always @(posedge i_clk) begin
-      c_r <= c & !i_clr;
+      //Clear carry when not in INIT state
+      c_r <= c & i_init;
 
       if (i_rst)
 	data <= 32'd0;
       else if (i_en)
-	data <= {i_loop ? o_q : q, data[31:1]};
+	data <= {(i_loop & !i_init) ? o_q : q, data[31:1]};
 
       if ((i_cnt[4:2] == 3'd0) & i_cnt_r[0] & i_en)
 	o_lsb[0] <= q;

rtl/serv_decode.v

@@ -112,7 +112,8 @@ module serv_decode
    assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]);
    assign o_bufreg_imm_en = !opcode[2];
 
-   assign o_bufreg_loop   = op_or_opimm & !(state == INIT);
+   //Set loop mode for shift operations
+   assign o_bufreg_loop   = op_or_opimm;
 
    assign o_ctrl_pc_en  = running | o_ctrl_trap;
 

rtl/serv_top.v

@@ -200,7 +200,7 @@ module serv_top
       .i_cnt    (cnt[4:2]),
       .i_cnt_r  (cnt_r[1:0]),
       .i_en     (!(bufreg_hold | o_dbus_cyc)),
-      .i_clr    (!init),
+      .i_init   (init),
       .i_loop   (bufreg_loop),
       .i_rs1    (rs1),
       .i_rs1_en (bufreg_rs1_en),