Expose with_csr in servant

rtl/serv_ctrl.v

@@ -53,7 +53,7 @@ module serv_ctrl
    assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
 
    generate
-      if (WITH_CSR)
+      if (|WITH_CSR)
 	assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
       else
 	assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;

rtl/serv_rf_if.v

@@ -53,7 +53,7 @@ module serv_rf_if
    wire 	     rd_wen = i_rd_wen & (|i_rd_waddr);
 
    generate
-   if (WITH_CSR) begin
+   if (|WITH_CSR) begin
    wire 	     rd = (i_ctrl_rd ) |
 			  (i_alu_rd & i_rd_alu_en) |
 			  (i_csr_rd & i_rd_csr_en) |

rtl/serv_top.v

@@ -222,7 +222,7 @@ module serv_top
 
    serv_state
      #(.RESET_STRATEGY (RESET_STRATEGY),
-       .WITH_CSR (WITH_CSR),
+       .WITH_CSR (WITH_CSR[0:0]),
        .MDU(MDU),
        .ALIGN(ALIGN))
    state
@@ -512,7 +512,7 @@ module serv_top
       .o_csr       (rf_csr_out));
 
    serv_mem_if
-     #(.WITH_CSR (WITH_CSR))
+     #(.WITH_CSR (WITH_CSR[0:0]))
    mem_if
      (
       .i_clk        (clk),
@@ -533,7 +533,7 @@ module serv_top
       .o_wb_sel     (o_dbus_sel));
 
    generate
-      if (WITH_CSR) begin
+      if (|WITH_CSR) begin
 	 serv_csr
 	   #(.RESET_STRATEGY (RESET_STRATEGY))
 	 csr

servant.core

@@ -463,6 +463,7 @@ targets:
       - vcd_start
       - compressed
       - align
+      - with_csr=1
     tools:
       verilator:
         verilator_options : [--trace]
@@ -568,6 +569,10 @@ parameters:
     description : Enable/Disable the Misaligned access of instruction
     paramtype   : vlogparam
   
+  with_csr:
+    datatype    : int
+    description : Enable/Disable CSR support
+    paramtype   : vlogparam
 
 generate:
   icebreaker_pll:

servant/servant.v

@@ -129,7 +129,7 @@ module servant
       .o_wb_ack (wb_mem_ack));
 
    generate
-      if (with_csr) begin
+      if (|with_csr) begin
 	 servant_timer
 	   #(.RESET_STRATEGY (reset_strategy),
 	     .WIDTH (32))