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break out verilator fileset for use with v < 4.030

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mtnrbq 2020-11-29 06:34:00 +11:00 committed by Olof Kindgren
parent aa16bc40b6
commit 75ee4954d0
1 changed files with 9 additions and 4 deletions
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13
servant.core
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@ -17,12 +17,17 @@ filesets:
servant_tb:
files:
- bench/servant_sim.v
- "!tool_verilator? (bench/uart_decoder.v)"
- "!tool_verilator? (bench/servant_tb.v)"
- "tool_verilator? (bench/servant_tb.cpp)" : {file_type : cppSource}
- bench/uart_decoder.v
- bench/servant_tb.v
file_type : verilogSource
depend : [vlog_tb_utils]
verilator_tb:
files:
- bench/servant_sim.v
- bench/servant_tb.cpp : {file_type : cppSource}
file_type : verilogSource
soc:
files:
- servant/servant_clock_gen.v
@ -281,7 +286,7 @@ targets:
verilator_tb:
default_tool: verilator
filesets : [soc, servant_tb]
filesets : [soc, verilator_tb]
parameters :
- RISCV_FORMAL
- firmware