chameleon96 board support added (#74)

* chameleon96 board added

README.md

@@ -145,6 +145,12 @@ blinky.hex change D10 to H5 (led[4]) in data/arty_a7_35t.xdc).
 
     fusesoc run --target=arty_a7_35t servant
 
+### Chameleon96 (Arrow 96 CV SoC Board)
+
+FPGA Pin W14 (1V8, pin 5 low speed connector) is used for UART Tx output with 115200 baud rate. No reset key. Yellow Wifi led is q output.
+
+    fusesoc run --target=chameleon96 servant
+
 ### DE0 Nano
 
 FPGA Pin D11 (Connector JP1, pin 38) is used for UART output with 57600 baud rate. DE0 Nano needs an external 3.3V UART to connect to this pin

data/chameleon96/CV_96.v

@@ -0,0 +1,28 @@
+
+module CV_96 (
+	output q,
+	output uart_txd
+);
+
+wire clk;		
+
+HPS   u0(
+	.h2f_user0_clk( clk)  	//hps_0_h2f_user0_clock.clk
+);
+	
+
+servive  u1 (
+	.i_clk   ( clk ), 
+	.i_rst_n ( 1'b1),
+	.q       ( q   ),
+	.uart_txd( uart_txd )
+);
+	  
+		   
+endmodule
+
+
+
+
+
+

data/chameleon96/HPS.sv

@@ -0,0 +1,108 @@
+
+module HPS(
+  output wire [1 - 1 : 0 ] h2f_rst_n
+ ,output wire [1 - 1 : 0 ] h2f_user0_clk
+);
+
+
+cyclonev_hps_interface_clocks_resets clocks_resets(
+ .f2h_pending_rst_ack({
+    1'b1 // 0:0
+  })
+,.f2h_warm_rst_req_n({
+    1'b1 // 0:0
+  })
+,.f2h_dbg_rst_req_n({
+    1'b1 // 0:0
+  })
+,.h2f_rst_n({
+    h2f_rst_n[0:0] // 0:0
+  })
+,.f2h_cold_rst_req_n({
+    1'b1 // 0:0
+  })
+,.h2f_user0_clk({
+    h2f_user0_clk[0:0] // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_dbg_apb debug_apb(
+ .DBG_APB_DISABLE({
+    1'b0 // 0:0
+  })
+,.P_CLK_EN({
+    1'b0 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_tpiu_trace tpiu(
+ .traceclk_ctl({
+    1'b1 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
+ .boot_from_fpga_ready({
+    1'b0 // 0:0
+  })
+,.boot_from_fpga_on_failure({
+    1'b0 // 0:0
+  })
+,.bsel_en({
+    1'b0 // 0:0
+  })
+,.csel_en({
+    1'b0 // 0:0
+  })
+,.csel({
+    2'b01 // 1:0
+  })
+,.bsel({
+    3'b001 // 2:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2hps fpga2hps(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_hps2fpga hps2fpga(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2sdram f2sdram(
+ .cfg_cport_rfifo_map({
+    18'b000000000000000000 // 17:0
+  })
+,.cfg_axi_mm_select({
+    6'b000000 // 5:0
+  })
+,.cfg_wfifo_cport_map({
+    16'b0000000000000000 // 15:0
+  })
+,.cfg_cport_type({
+    12'b000000000000 // 11:0
+  })
+,.cfg_rfifo_cport_map({
+    16'b0000000000000000 // 15:0
+  })
+,.cfg_port_width({
+    12'b000000000000 // 11:0
+  })
+,.cfg_cport_wfifo_map({
+    18'b000000000000000000 // 17:0
+  })
+);
+
+endmodule
+

data/chameleon96/chain1.cdf

@@ -0,0 +1,15 @@
+/* Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Ign)
+		Device PartName(SOCVHPS) MfrSpec(OpMask(0));
+	P ActionCode(Cfg)
+		Device PartName(5CSEBA6U19) Path("/home/jordi/bin/fusesoc/build/fusesoc_utils_blinky_1.1/chameleon96-quartus/") File("fusesoc_utils_blinky_1_1.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

data/chameleon96/chameleon96.sdc

@@ -0,0 +1,8 @@
+# Main system clock (100 Mhz)
+create_clock -name "clk" -period 10.000ns [get_pins -compatibility_mode u0|clocks_resets|h2f_user0_clk]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

data/chameleon96/pinmap.tcl

@@ -0,0 +1,20 @@
+#
+# Clock / Reset
+#
+# set_location_assignment PIN_xxxx -to i_clk
+# No direct clock. Using internal HPS clock
+
+#
+# GPIO
+#
+# LED  Y19 Yellow WIFI, Y20 Blue Bluetooth
+set_location_assignment PIN_Y19 -to q
+set_instance_assignment -name IO_STANDARD "2.5 V" -to q
+
+# FPGA_1V8_HPS_EXP_UART1_TXD_PIN_W14      Pin 5  Low speed connector  (WHITE C96 USB/serial cable)    Pin 1 GND
+set_location_assignment PIN_W14 -to uart_txd
+set_instance_assignment -name IO_STANDARD "1.8 V" -to uart_txd
+
+# No reset button wired to FPGA
+# set_location_assignment PIN_xxx -to i_rst_n
+

servant.core

@@ -57,6 +57,15 @@ filesets:
       - servant/servive_clock_gen.v : {file_type : verilogSource}
       - servant/servive.v : {file_type : verilogSource}
 
+  chameleon96:
+    files:
+      - data/chameleon96/chameleon96.sdc : {file_type : SDC}
+      - data/chameleon96/pinmap.tcl   : {file_type: tclSource}
+      - data/chameleon96/HPS.sv : {file_type : systemVerilogSource}
+      - data/chameleon96/CV_96.v : {file_type : verilogSource}
+      - servant/servive_clock_gen.v : {file_type : verilogSource}
+      - servant/servive.v : {file_type : verilogSource}    
+      
   deca:
     files:
       - data/deca.sdc : {file_type : SDC}
@@ -180,6 +189,17 @@ targets:
         device : 5CSXFC6D6F31C6
     toplevel: servive
 
+  chameleon96:
+    default_tool : quartus
+    description : Chameleon96 (Arrow 96 CV SoC Board)
+    filesets : [mem_files, soc, chameleon96]
+    parameters : [memfile, memsize]
+    tools:
+      quartus:
+        family : Cyclone V
+        device : 5CSEBA6U19I7
+    toplevel: CV_96
+    
   deca:
     default_tool : quartus
     description: DECA development kit by Arrow / Terasic