synthesized netlist works

bench/serv_soc_tb.cpp

@@ -28,11 +28,13 @@ int main(int argc, char **argv, char **env)
 	uint32_t insn = 0;
 	uint32_t ex_pc = 0;
 
+	int uart_state = 0;
+	char uart_ch = 0;
 	Verilated::commandArgs(argc, argv);
 
 	Vserv_wrapper* top = new Vserv_wrapper;
 
-	//const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
+	const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
 	//if (vcd[0]) == '\0' || atoi(arg + 11) != 0)
 	Verilated::traceEverOn(true);
         VerilatedVcdC* tfp = new VerilatedVcdC;
@@ -42,12 +44,16 @@ int main(int argc, char **argv, char **env)
 	signal(SIGINT, INThandler);
 
 	top->wb_clk = 1;
-
+	bool q = top->q;
 	while (!(done || Verilated::gotFinish())) {
 	  top->eval();
 	  tfp->dump(main_time);
+	  if (q != top->q) {
+	    q = top->q;
+	    printf("%lu output is %s\n", main_time, q ? "ON" : "OFF");
+	  }
 	  top->wb_clk = !top->wb_clk;
-	  main_time+=5;
+	  main_time+=31.25;
 	}
 	tfp->close();
 	exit(0);

bench/serv_top_tb.v

@@ -1,16 +1,23 @@
 `default_nettype none
 module serv_top_tb;
 
-   parameter firmware = "firmware.hex";
+   parameter memfile = "bitbang.hex";
 
    reg wb_clk = 1'b1;
-   reg wb_rst = 1'b1;
 
-   always #5 wb_clk <= !wb_clk;
-   initial #100 wb_rst = 1'b0;
+   reg q_r = 1'b0;
+   wire q;
+
+   always #31 wb_clk <= !wb_clk;
 
    vlog_tb_utils vtu();
 
-   serv_wrapper #(firmware) dut(wb_clk, wb_rst);
+   serv_wrapper #(memfile) dut(wb_clk, q);
+
+   always @(posedge wb_clk)
+     if (q != q_r) begin
+	$display("%0t : q is %s", $time, q ? "ON" : "OFF");
+	q_r <= q;
+     end
 
 endmodule

bench/serv_wrapper.v

@@ -1,12 +1,12 @@
 `default_nettype none
 module serv_wrapper
 (
- input wire wb_clk);
+ input wire  wb_clk,
+ output wire q);
 
 //   parameter memfile = "hellomin.hex";
    parameter memfile = "bitbang.hex";
 
-
    reg [4:0] rst_reg = 5'b11111;
 
    always @(posedge wb_clk)
@@ -18,7 +18,7 @@ module serv_wrapper
 
 `include "wb_intercon.vh"
 
-   localparam MEMORY_SIZE = 16384*4;
+   localparam MEMORY_SIZE = 2048*4;
 
 `ifndef SYNTHESIS
 //synthesis translate_off
@@ -63,7 +63,7 @@ module serv_wrapper
       .o_wb_ack   (wb_s2m_testprint_ack));
 
    assign wb_s2m_testprint_dat = 32'h0;
-   
+
    testhalt testhalt
      (
       .i_wb_clk   (wb_clk),
@@ -87,11 +87,21 @@ module serv_wrapper
       .o_wb_dat (wb_s2m_timer_dat),
       .o_wb_ack (wb_s2m_timer_ack));
 
+   wb_gpio gpio
+     (.i_wb_clk (wb_clk),
+      .i_wb_dat (wb_m2s_gpio_dat[0]),
+      .i_wb_cyc (wb_m2s_gpio_cyc),
+      .o_wb_ack (wb_s2m_gpio_ack),
+      .o_gpio   (q));
+
+   assign wb_s2m_gpio_dat = 32'h0;
+
    serv_top
-     #(.RESET_PC (32'h8000_0000))
+     #(.RESET_PC (32'h0000_0000))
    cpu
      (
       .clk      (wb_clk),
+      .i_rst    (wb_rst),
       .o_ibus_adr   (wb_m2s_cpu_ibus_adr),
       .o_ibus_cyc   (wb_m2s_cpu_ibus_cyc),
       .o_ibus_stb   (wb_m2s_cpu_ibus_stb),

data/tinyfpga_bx.pcf

@@ -0,0 +1,2 @@
+set_io q B3
+set_io wb_clk B2

rtl/serv_ctrl.v

@@ -2,6 +2,7 @@
 module serv_ctrl
   (
    input wire 	      clk,
+   input wire 	      i_rst,
    input wire 	      i_en,
    input wire 	      i_pc_en,
    input wire 	      i_cnt_done,
@@ -16,7 +17,7 @@ module serv_ctrl
    output wire 	      o_bad_pc,
    output reg 	      o_misalign = 1'b0,
    output wire [31:0] o_ibus_adr,
-   output reg 	      o_ibus_cyc = 1'b0,
+   output reg 	      o_ibus_cyc,
    input wire 	      i_ibus_ack);
 
    parameter RESET_PC = 32'd8;
@@ -76,12 +77,12 @@ module serv_ctrl
    wire       pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
 
 
-   reg        en_r  = 1'b0;
-   reg        en_2r = 1'b0;
-   reg        en_3r = 1'b0;
-   reg 	      en_pc_r = 1'b1;
-   reg 	      en_pc_2r = 1'b0;
-   reg 	      en_pc_3r = 1'b0;
+   reg        en_r;
+   reg        en_2r;
+   reg        en_3r;
+   reg 	      en_pc_r;
+   reg 	      en_pc_2r;
+   reg 	      en_pc_3r;
 
    always @(posedge clk) begin
       en_r <= i_en;
@@ -97,6 +98,15 @@ module serv_ctrl
         o_ibus_cyc <= 1'b1;
       else if (o_ibus_cyc & i_ibus_ack)
         o_ibus_cyc <= 1'b0;
+      if (i_rst) begin
+	 en_r  <= 1'b0;
+	 en_2r <= 1'b0;
+	 en_3r <= 1'b0;
+	 en_pc_r <= 1'b1;
+	 en_pc_2r <= 1'b0;
+	 en_pc_3r <= 1'b0;
+	 o_ibus_cyc <= 1'b0;
+      end
    end
 
 endmodule

rtl/serv_decode.v

@@ -2,6 +2,7 @@
 module serv_decode
   (
    input wire 	     clk,
+   input wire 	     i_rst,
    input wire [31:0] i_wb_rdt,
    input wire 	     i_wb_en,
    output wire 	     o_cnt_done,
@@ -69,6 +70,7 @@ module serv_decode
      OP_SYSTEM = 5'b11100;
 
    reg [1:0]    state = IDLE;
+   reg 		go;
 
    reg [4:0] cnt     = 5'd0;
 
@@ -134,7 +136,7 @@ module serv_decode
    assign o_csr_en = ((((opcode == OP_SYSTEM) & (|o_funct3)) |
 		     o_ctrl_mret) & running) | o_ctrl_trap;
 
-   always @(o_funct3) begin
+   always @(o_funct3, imm) begin
       casez (o_funct3)
         3'b00?  : o_alu_cmp_sel = ALU_CMP_EQ;
         3'b01?  : o_alu_cmp_sel = ALU_CMP_LT;
@@ -284,9 +286,11 @@ module serv_decode
         else              o_imm = imm[cnt+7];
    end
 
-   reg go = 1'b0;
-   always @(posedge clk)
-     go <= i_wb_en;
+   always @(posedge clk) begin
+      go <= i_wb_en;
+      if (i_rst)
+	go <= 1'b0;
+   end
 
    wire cnt_en = (state != IDLE);
 
@@ -341,6 +345,15 @@ module serv_decode
 
       cnt <= cnt + {4'd0,cnt_en};
 
+      if (i_rst) begin
+	 //output reg [2:0]  o_funct3,
+	 //output reg 	     o_imm,
+	 state <= IDLE;
+	 cnt   <= 5'd0;
+	 //reg       signbit;
+	 //reg [4:0] opcode;
+	 //reg [31:0] imm;
+      end
    end
 //`define SERV_DECODE_CHECKS
 `ifdef SERV_DECODE_CHECKS

rtl/serv_top.v

@@ -9,6 +9,7 @@
 module serv_top
   (
    input wire 	      clk,
+   input wire 	      i_rst,
 `ifdef RISCV_FORMAL
    output reg 	      rvfi_valid = 1'b0,
    output reg [63:0]  rvfi_order = 64'd0,
@@ -118,6 +119,7 @@ module serv_top
    serv_decode decode
      (
       .clk (clk),
+      .i_rst          (i_rst),
       .i_wb_rdt       (i_ibus_rdt),
       .i_wb_en        (o_ibus_cyc & i_ibus_ack),
       .o_cnt_done     (cnt_done),
@@ -169,6 +171,7 @@ module serv_top
    ctrl
      (
       .clk        (clk),
+      .i_rst      (i_rst),
       .i_en       (ctrl_en),
       .i_pc_en    (ctrl_pc_en),
       .i_cnt_done (cnt_done),

rtl/wb_gpio.v

@@ -0,0 +1,14 @@
+module wb_gpio
+  (
+   input wire i_wb_clk,
+   input wire i_wb_dat,
+   input wire i_wb_cyc,
+   output reg o_wb_ack = 1'b0,
+   output reg o_gpio = 1'b0);
+   
+   always @(posedge i_wb_clk)
+     if (i_wb_cyc) begin
+	o_wb_ack <= ~o_wb_ack;
+	o_gpio <= i_wb_dat;
+     end
+endmodule

serv.core

@@ -20,23 +20,39 @@ filesets:
       - rtl/serv_top.v
     file_type : verilogSource
 
+  mem_files:
+    files:
+      - bitbang.hex  : {copyto : bitbang.hex}
+      - hellomin.hex : {copyto : hellomin.hex}
+    file_type : user
+      
+  pcf:
+    files:
+      - data/dummy.pcf : {file_type : PCF}
   serv_top_tb:
     files:
       - bench/serv_top_tb.v
     file_type : verilogSource
     depend : [vlog_tb_utils, "yosys:techlibs:ice40"]
 
+  techlib:
+    depend : ["yosys:techlibs:ice40fork"]
   wrapper:
     files:
       - testhalt.v
       - testprint.v
       - rtl/riscv_timer.v
+      - rtl/wb_gpio.v
       - bench/serv_wrapper.v
     file_type : verilogSource
     depend : [wb_intercon, wb_ram]
 
-  pcf:
-    files: [data/dummy.pcf : {file_type : PCF}]
+  netlist:
+    files: [synth.v : {file_type : verilogSource}]
+
+  tinyfpga_bx:
+    files:
+      - data/tinyfpga_bx.pcf : {file_type : PCF}
 
   verilator_tb:
     files:
@@ -50,12 +66,23 @@ targets:
 
   synth:
     default_tool : icestorm
-    filesets : [core, pcf]
-    toplevel : serv_top
+    filesets : [core, wrapper, pcf]
+    generate : [wb_intercon]
+    toplevel : serv_wrapper
+
+  tinyfpga_bx:
+    default_tool : icestorm
+    filesets : [core, wrapper, tinyfpga_bx]
+    generate : [wb_intercon]
+    tools:
+      icestorm:
+        nextpnr_options : [--lp8k, --package, cm81, --freq, 16]
+        pnr: next
+    toplevel : serv_wrapper
 
   lint:
     default_tool : verilator
-    filesets : [core]
+    filesets : [core, techlib]
     tools:
       verilator:
         mode : lint-only
@@ -68,6 +95,11 @@ targets:
     parameters : [RISCV_FORMAL=true, firmware]
     toplevel : serv_top_tb
 
+  synth_tb:
+    default_tool: icarus
+    filesets : [netlist, serv_top_tb]
+    toplevel : serv_top_tb
+
   verilator_tb:
     default_tool: verilator
     filesets : [core, wrapper, verilator_tb]
@@ -99,10 +131,10 @@ generate:
         cpu_ibus:
           slaves : [mem]
         cpu_dbus:
-          slaves : [mem, testprint, testhalt, timer]
+          slaves : [mem, testprint, testhalt, gpio, timer]
       slaves:
         mem:
-          offset : 0x80000000
+          offset : 0x00000000
           size   : 65536
         testprint:
           offset : 0x10000000
@@ -110,6 +142,9 @@ generate:
         testhalt:
           offset : 0x20000000
           size   : 4
+        gpio:
+          offset : 0x30000000
+          size   : 4
         timer:
           offset : 0xf00fff40
           size   : 16