Add reset input for Arty A7 target

data/arty_a7_35t.xdc

@@ -1,5 +1,7 @@
 set_property -dict {PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports i_clk];
 
+set_property -dict {PACKAGE_PIN C2  IOSTANDARD LVCMOS33 } [get_ports i_rst_n];
+
 set_property -dict {PACKAGE_PIN D10  IOSTANDARD LVCMOS33 } [get_ports q]
 
 #set_property -dict {PACKAGE_PIN H5  IOSTANDARD LVCMOS33 } [get_ports q]

servant.core

@@ -382,7 +382,7 @@ targets:
   arty_a7_35t:
     default_tool: vivado
     filesets : [mem_files, soc, arty_a7_35t]
-    parameters : [memfile, memsize, frequency=16, "mdu? (MDU=1)"]
+    parameters : [memfile, memsize, frequency=16, "mdu? (MDU=1)", WITH_RESET]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : servix
@@ -586,6 +586,11 @@ parameters:
     description : Enable/Disable CSR support
     paramtype   : vlogparam
 
+  WITH_RESET:
+    datatype    : bool
+    default     : true
+    description : Enable reset input (for supported targets)
+    paramtype   : vlogdefine
 generate:
   icebreaker_pll:
     generator: icepll

servant/servix.v

@@ -2,6 +2,9 @@
 module servix
 (
  input wire  i_clk,
+`ifdef WITH_RESET
+ input wire  i_rst_n,
+`endif
  output wire q);
 
    parameter frequency = 32;
@@ -16,6 +19,11 @@ module servix
      #(.frequency (frequency))
    clock_gen
      (.i_clk (i_clk),
+`ifdef WITH_RESET
+      .i_rst (!i_rst_n),
+`else
+      .i_rst (1'b0),
+`endif
       .o_clk (wb_clk),
       .o_rst (wb_rst));
 

servant/servix_clock_gen.v

@@ -1,6 +1,7 @@
 `default_nettype none
 module servix_clock_gen
   (input wire  i_clk,
+   input wire  i_rst,
    output wire o_clk,
    output reg  o_rst);
 
@@ -28,7 +29,7 @@ module servix_clock_gen
       .LOCKED(locked),
       .CLKIN1(i_clk),
       .PWRDWN(1'b0),
-      .RST(1'b0),
+      .RST(i_rst),
       .CLKFBIN(clkfb));
 
    always @(posedge o_clk) begin