github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-01-11 23:42:50 +00:00
Code Issues Releases Wiki Activity

Update reamde, comments and paramters

Browse Source
This commit is contained in:
Abd 2022-05-31 00:18:14 +05:00 committed by Olof Kindgren
parent 2655861447
commit 82b410f500
3 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README.md
View File

@ -84,6 +84,10 @@ To build the verilator model with MDU (for M extension compliance tests):
fusesoc run --target=verilator_tb --flag=mdu --build servant --memsize=8388608
To build the verilator model with C extension (for Compressed extension compliance tests):
fusesoc run --target=verilator_tb --build servant --memsize=8388608 --compressed=1
Download the tests repo
git clone https://github.com/riscv-non-isa/riscv-arch-test.git

2
rtl/serv_ctrl.v
View File

@ -44,6 +44,8 @@ module serv_ctrl
wire offset_a;
wire offset_b;
/* If i_iscomp=1: increment pc by 2 else increment pc by 4 */
assign plus_4 = i_iscomp ? i_cnt1 : i_cnt2;
assign o_bad_pc = pc_plus_offset_aligned;

2
rtl/serv_rf_top.v
View File

@ -10,7 +10,7 @@ module serv_rf_top
ALIGN = 1: Fetch the aligned instruction by making two bus transactions if the misaligned address
is given to the instruction bus.
*/
parameter [0:0] ALIGN = 0,
parameter [0:0] ALIGN = COMPRESSED,
/* Multiplication and Division Unit
This parameter enables the interface for connecting SERV and MDU
*/