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Code Issues Releases Wiki Activity

updated vars declaration for modelsim (#63)

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This commit is contained in:
Zeeshan Rafique
2021-10-04 02:15:54 +05:00
committed by GitHub
parent 48e250ea5e
commit 8843005407
3 changed files with 10 additions and 9 deletions
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12
rtl/serv_decode.v
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@@ -77,6 +77,12 @@ generate
wire co_mem_word;
wire co_rd_alu_en;
//opcode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2];
if (MDU) begin
assign co_mdu_op = ((opcode == 5'b01100) & imm25);
assign co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
@@ -93,12 +99,6 @@ generate
assign co_ext_funct3 = funct3;
endgenerate
//opcode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2];
//jal,branch = imm
//jalr = rs1+imm
//mem = rs1+imm

3
rtl/serv_immdec.v
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@@ -28,7 +28,6 @@ module serv_immdec
reg [4:0] imm24_20;
reg [4:0] imm11_7;
assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0];
assign o_csr_imm = imm19_12_20[4];
wire signbit = imm31 & !i_csr_imm_en;
@@ -90,5 +89,7 @@ module serv_immdec
end
end
endgenerate
assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0];
endmodule

4
rtl/serv_top.v
View File

@@ -121,6 +121,8 @@ module serv_top
wire bufreg_imm_en;
wire bufreg_clr_lsb;
wire bufreg_q;
wire [31:0] dbus_rdt;
wire dbus_ack;
wire alu_sub;
wire [1:0] alu_bool_op;
@@ -566,8 +568,6 @@ module serv_top
`endif
generate
wire [31:0] dbus_rdt;
wire dbus_ack;
if (MDU) begin
assign dbus_rdt = i_ext_ready ? i_ext_rd:i_dbus_rdt;
assign dbus_ack = i_dbus_ack | i_ext_ready;