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Code Issues Releases Wiki Activity

updated vars declaration for modelsim (#63)

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This commit is contained in:
Zeeshan Rafique
2021-10-04 02:15:54 +05:00
committed by GitHub
parent 48e250ea5e
commit 8843005407
3 changed files with 10 additions and 9 deletions
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12
rtl/serv_decode.v
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@@ -77,6 +77,12 @@ generate
wire co_mem_word;
wire co_rd_alu_en;
//opcode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2];
if (MDU) begin
assign co_mdu_op = ((opcode == 5'b01100) & imm25);
assign co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
@@ -93,12 +99,6 @@ generate
assign co_ext_funct3 = funct3;
endgenerate
//opcode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2];
//jal,branch = imm
//jalr = rs1+imm
//mem = rs1+imm