Syntax and reset fixes for ModelSim

bench/servant_tb.v

@@ -8,6 +8,8 @@ module servant_tb;
    reg wb_clk = 1'b0;
    reg wb_rst = 1'b1;
 
+   wire q;
+
    always  #31 wb_clk <= !wb_clk;
    initial #62 wb_rst <= 1'b0;
 

rtl/serv_ctrl.v

@@ -1,6 +1,8 @@
 `default_nettype none
 module serv_ctrl
-  #(parameter RESET_STRATEGY = "MINI")
+  #(parameter RESET_STRATEGY = "MINI",
+    parameter RESET_PC = 32'd0,
+    parameter WITH_CSR = 1)
   (
    input wire 	      clk,
    input wire 	      i_rst,
@@ -26,9 +28,6 @@ module serv_ctrl
    output wire 	      o_ibus_cyc,
    input wire 	      i_ibus_ack);
 
-   parameter RESET_PC = 32'd0;
-   parameter WITH_CSR = 1;
-
    reg 	      en_pc_r;
 
    wire       pc_plus_4;

rtl/serv_state.v

@@ -1,5 +1,6 @@
 module serv_state
-  #(parameter RESET_STRATEGY = "MINI")
+  #(parameter RESET_STRATEGY = "MINI",
+    parameter [0:0] WITH_CSR = 1)
   (
    input wire 	     i_clk,
    input wire 	     i_rst,
@@ -42,8 +43,6 @@ module serv_state
    output reg 	     o_cnt_done,
    output wire 	     o_bufreg_hold);
 
-   parameter [0:0] WITH_CSR = 1;
-
    wire 	     cnt4;
 
    reg 	stage_two_req;
@@ -129,6 +128,7 @@ module serv_state
 
       if (i_rst) begin
 	 if (RESET_STRATEGY != "NONE") begin
+	    o_cnt_en <= 1'b0;
 	    o_cnt   <= 3'd0;
 	    stage_two_pending <= 1'b0;
 	    o_ctrl_jump <= 1'b0;
@@ -158,6 +158,13 @@ module serv_state
 	misalign_trap_sync <= trap_pending;
       if (i_ibus_ack)
 	misalign_trap_sync <= 1'b0;
+      if (i_rst)
+	if (RESET_STRATEGY != "NONE") begin
+	   misalign_trap_sync <= 1'b0;
+	   irq_sync           <= 1'b0;
+	   o_pending_irq      <= 1'b0;
+	end
+
    end // always @ (posedge i_clk)
       end else begin
 	 assign o_trap_taken = 0;

rtl/serv_top.v

@@ -125,7 +125,6 @@ module serv_top
    wire          rd_en;
 
    wire          op_b_source;
-   wire          op_b;
 
    wire          mem_signed;
    wire          mem_word;

servant/servant.v

@@ -105,10 +105,12 @@ module servant
 
    servant_ram
      #(.memfile (memfile),
-       .depth (memsize))
+       .depth (memsize),
+       .RESET_STRATEGY (reset_strategy))
    ram
      (// Wishbone interface
       .i_wb_clk (wb_clk),
+      .i_wb_rst (wb_rst),
       .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
       .i_wb_cyc (wb_mem_cyc),
       .i_wb_we  (wb_mem_we) ,
@@ -120,9 +122,11 @@ module servant
    generate
       if (with_csr) begin
 	 servant_timer
-	   #(.WIDTH (32))
+	   #(.RESET_STRATEGY (reset_strategy),
+	     .WIDTH (32))
 	 timer
 	   (.i_clk    (wb_clk),
+	    .i_rst    (wb_rst),
 	    .o_irq    (timer_irq),
 	    .i_wb_cyc (wb_timer_cyc),
 	    .i_wb_we  (wb_timer_we) ,

servant/servant_ram.v

@@ -3,8 +3,10 @@ module servant_ram
   #(//Memory parameters
     parameter depth = 256,
     parameter aw    = $clog2(depth),
+    parameter RESET_STRATEGY = "",
     parameter memfile = "")
    (input wire 		i_wb_clk,
+    input wire 		i_wb_rst,
     input wire [aw-1:2] i_wb_adr,
     input wire [31:0] 	i_wb_dat,
     input wire [3:0] 	i_wb_sel,
@@ -20,7 +22,10 @@ module servant_ram
    wire [aw-3:0] 	addr = i_wb_adr[aw-1:2];
 
    always @(posedge i_wb_clk)
-     o_wb_ack <= i_wb_cyc & !o_wb_ack;
+     if (i_wb_rst & (RESET_STRATEGY != "NONE"))
+       o_wb_ack <= 1'b0;
+     else
+       o_wb_ack <= i_wb_cyc & !o_wb_ack;
 
    always @(posedge i_wb_clk) begin
       if (we[0]) mem[addr][7:0]   <= i_wb_dat[7:0];

servant/servant_timer.v

@@ -1,8 +1,10 @@
 `default_nettype none
 module servant_timer
   #(parameter WIDTH = 16,
+    parameter RESET_STRATEGY = "",
     parameter DIVIDER = 0)
   (input wire 	     i_clk,
+   input wire 	     i_rst,
    output reg 	     o_irq,
    input wire [31:0] i_wb_dat,
    input wire 	     i_wb_we,
@@ -26,5 +28,10 @@ module servant_timer
 	mtimecmp <= i_wb_dat[HIGH:0];
       mtime <= mtime + 'd1;
       o_irq <= (mtimeslice >= mtimecmp);
+      if (RESET_STRATEGY != "NONE")
+	if (i_rst) begin
+	   mtime <= 0;
+	   mtimecmp <= 0;
+	end
    end
 endmodule