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Syntax and reset fixes for ModelSim

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Olof Kindgren
2020-11-10 15:13:04 +01:00
parent c1b8471678
commit 90ce4ff1af
7 changed files with 34 additions and 11 deletions
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bench/servant_tb.v
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@@ -8,6 +8,8 @@ module servant_tb;
reg wb_clk = 1'b0;
reg wb_rst = 1'b1;
wire q;
always #31 wb_clk <= !wb_clk;
initial #62 wb_rst <= 1'b0;