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Code Issues Releases Wiki Activity

Syntax and reset fixes for ModelSim

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This commit is contained in:
Olof Kindgren
2020-11-10 15:13:04 +01:00
parent c1b8471678
commit 90ce4ff1af
7 changed files with 34 additions and 11 deletions
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7
rtl/serv_ctrl.v
View File

@@ -1,6 +1,8 @@
`default_nettype none
module serv_ctrl
#(parameter RESET_STRATEGY = "MINI")
#(parameter RESET_STRATEGY = "MINI",
parameter RESET_PC = 32'd0,
parameter WITH_CSR = 1)
(
input wire clk,
input wire i_rst,
@@ -26,9 +28,6 @@ module serv_ctrl
output wire o_ibus_cyc,
input wire i_ibus_ack);
parameter RESET_PC = 32'd0;
parameter WITH_CSR = 1;
reg en_pc_r;
wire pc_plus_4;

13
rtl/serv_state.v
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@@ -1,5 +1,6 @@
module serv_state
#(parameter RESET_STRATEGY = "MINI")
#(parameter RESET_STRATEGY = "MINI",
parameter [0:0] WITH_CSR = 1)
(
input wire i_clk,
input wire i_rst,
@@ -42,8 +43,6 @@ module serv_state
output reg o_cnt_done,
output wire o_bufreg_hold);
parameter [0:0] WITH_CSR = 1;
wire cnt4;
reg stage_two_req;
@@ -129,6 +128,7 @@ module serv_state
if (i_rst) begin
if (RESET_STRATEGY != "NONE") begin
o_cnt_en <= 1'b0;
o_cnt <= 3'd0;
stage_two_pending <= 1'b0;
o_ctrl_jump <= 1'b0;
@@ -158,6 +158,13 @@ module serv_state
misalign_trap_sync <= trap_pending;
if (i_ibus_ack)
misalign_trap_sync <= 1'b0;
if (i_rst)
if (RESET_STRATEGY != "NONE") begin
misalign_trap_sync <= 1'b0;
irq_sync <= 1'b0;
o_pending_irq <= 1'b0;
end
end // always @ (posedge i_clk)
end else begin
assign o_trap_taken = 0;

1
rtl/serv_top.v
View File

@@ -125,7 +125,6 @@ module serv_top
wire rd_en;
wire op_b_source;
wire op_b;
wire mem_signed;
wire mem_word;