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Code Issues Releases Wiki Activity

Remove unused rs_en signal

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This commit is contained in:
Olof Kindgren 2019-09-16 10:45:42 +02:00
parent 6518b5f30f
commit 920ad92bc7
2 changed files with 3 additions and 5 deletions
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3
rtl/serv_state.v
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@ -22,7 +22,6 @@ module serv_state
output reg o_ctrl_jump,
output wire o_ctrl_trap,
input wire i_ctrl_misalign,
output wire o_rf_rs_en,
output wire o_alu_shamt_en,
input wire i_alu_sh_done,
output wire o_dbus_cyc,
@ -82,8 +81,6 @@ module serv_state
reg pending_irq;
assign o_rf_rs_en = two_stage_op ? (state == INIT) : o_ctrl_pc_en;
assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign;
always @(posedge i_clk) begin

5
rtl/serv_top.v
View File

@ -101,7 +101,6 @@ module serv_top
wire rf_ready;
wire rs1;
wire rs2;
wire rs_en;
wire rd_en;
wire op_b_source;
@ -161,7 +160,6 @@ module serv_top
.i_ctrl_misalign(lsb[1]),
.o_alu_shamt_en (alu_shamt_en),
.i_alu_sh_done (alu_sh_done),
.o_rf_rs_en (rs_en),
.o_dbus_cyc (o_dbus_cyc),
.o_mem_bytecnt (mem_bytecnt),
.i_mem_misalign (mem_misalign),
@ -394,6 +392,8 @@ module serv_top
`ifdef RISCV_FORMAL
reg [31:0] pc = RESET_PC;
wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en;
always @(posedge clk) begin
rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst;
rvfi_order <= rvfi_order + {63'd0,rvfi_valid};
@ -445,6 +445,7 @@ module serv_top
rvfi_pc_wdata <= o_ibus_adr;
/* verilator lint_on COMBDLY */
`endif
endmodule