Inline shift_reg

rtl/serv_alu.v

@@ -31,7 +31,7 @@ module serv_alu
 
    reg 	       result_lt_r;
 
-   wire [4:0]  shamt;
+   reg [4:0]   shamt;
    reg 	       shamt_msb;
 
    wire        shamt_ser;
@@ -47,14 +47,6 @@ module serv_alu
    wire op_b = i_op_b_rs2 ? i_rs2 : i_imm;
    assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1;
 
-   shift_reg #(.LEN (5)) shamt_reg
-     (.clk (clk),
-      .i_rst (i_rst),
-      .i_en (i_shamt_en),
-      .i_d  (shamt_ser),
-      .o_q  (shamt[0]),
-      .o_par (shamt[4:1]));
-
    ser_shift shift
      (
       .i_clk (clk),
@@ -105,8 +97,10 @@ module serv_alu
       end
       eq_r <= result_eq | ~i_en;
 
-      if (i_shamt_en)
-	shamt_msb <= b_inv_plus_1_cy;
+      if (i_shamt_en) begin
+	 shamt_msb <= b_inv_plus_1_cy;
+	 shamt <= {shamt_ser,shamt[4:1]};
+      end
    end
 
 endmodule

rtl/serv_ctrl.v

@@ -21,7 +21,7 @@ module serv_ctrl
    output wire 	      o_rd,
    output wire 	      o_bad_pc,
    //External
-   output wire [31:0] o_ibus_adr,
+   output reg [31:0] o_ibus_adr,
    output wire 	      o_ibus_cyc,
    input wire 	      i_ibus_ack);
 
@@ -39,7 +39,7 @@ module serv_ctrl
    wire       pc_plus_offset_aligned;
    wire       plus_4;
 
-   wire       pc;
+   wire       pc = o_ibus_adr[0];
 
    wire       new_pc;
 
@@ -48,25 +48,10 @@ module serv_ctrl
 
    assign plus_4        = i_cnt2;
 
-   assign o_ibus_adr[0] = pc;
    assign o_bad_pc = pc_plus_offset_aligned;
 
    assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
 
-   shift_reg
-     #(
-       .LEN  (32),
-       .INIT (RESET_PC))
-   pc_reg
-     (
-      .clk (clk),
-      .i_rst (i_rst),
-      .i_en (i_pc_en),
-      .i_d  (new_pc),
-      .o_q  (pc),
-      .o_par (o_ibus_adr[31:1])
-      );
-
    generate
       if (WITH_CSR)
 	assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
@@ -87,13 +72,15 @@ module serv_ctrl
       pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
       pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
 
-      if (i_pc_en)
-	en_pc_r <= 1'b1;
-      else if (o_ibus_cyc & i_ibus_ack)
+      if (i_pc_en) begin
+	 en_pc_r <= 1'b1;
+	 o_ibus_adr <= {new_pc, o_ibus_adr[31:1]};
+      end else if (o_ibus_cyc & i_ibus_ack)
         en_pc_r <= 1'b0;
 
       if (i_rst) begin
 	 en_pc_r <= 1'b1;
+	 o_ibus_adr <= RESET_PC;
       end
    end
 

rtl/shift_reg.v

@@ -1,20 +0,0 @@
-module shift_reg
-  #(parameter LEN = 0,
-    parameter INIT = 0)
-  (
-   input wire 		 clk,
-   input wire 		 i_rst,
-   input wire 		 i_en,
-   input wire 		 i_d,
-   output wire 		 o_q,
-   output wire [LEN-2:0] o_par);
-
-   reg [LEN-1:0] 	 data;
-   assign o_q = data[0];
-   assign o_par = data[LEN-1:1];
-   always @(posedge clk)
-     if (i_rst)
-       data <= INIT;
-     else if (i_en)
-       data <= {i_d, data[LEN-1:1]};
-endmodule

serv.core

@@ -6,7 +6,6 @@ filesets:
   core:
     files:
       - rtl/serv_params.vh : {is_include_file : true}
-      - rtl/shift_reg.v
       - rtl/ser_shift.v
       - rtl/serv_bufreg.v
       - rtl/serv_alu.v