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Replace mem_op with dedicated control signals

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This commit is contained in:
Olof Kindgren 2021-10-05 09:29:06 +02:00
parent e5c6e78820
commit 9d3ebf3e96
5 changed files with 45 additions and 25 deletions
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23
rtl/serv_decode.v
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@ -14,10 +14,11 @@ module serv_decode
output reg o_e_op,
output reg o_ebreak,
output reg o_branch_op,
output reg o_mem_op,
output reg o_shift_op,
output reg o_slt_op,
output reg o_rd_op,
output reg o_two_stage_op,
output reg o_dbus_en,
//MDU
output reg o_mdu_op,
//Extension
@ -52,10 +53,13 @@ module serv_decode
output reg [1:0] o_csr_source,
output reg o_csr_d_sel,
output reg o_csr_imm_en,
output reg o_mtval_pc,
//To top
output reg [3:0] o_immdec_ctrl,
output reg [3:0] o_immdec_en,
output reg o_op_b_source,
//To RF IF
output reg o_rd_mem_en,
output reg o_rd_csr_en,
output reg o_rd_alu_en);
@ -72,12 +76,17 @@ module serv_decode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
wire co_mdu_op = MDU & (opcode == 5'b01100) & imm25;
wire co_two_stage_op =
~opcode[2] | (funct3[0] & ~funct3[1] & ~opcode[0] & ~opcode[4]) |
(funct3[1] & ~funct3[2] & ~opcode[0] & ~opcode[4]) | co_mdu_op;
wire co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
wire co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2];
wire co_dbus_en = ~opcode[2] & ~opcode[4];
wire co_mtval_pc = opcode[4];
wire co_mem_word = funct3[1];
wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
wire co_rd_mem_en = (!opcode[2] & !opcode[0]) | co_mdu_op;
wire [2:0] co_ext_funct3 = funct3;
//jal,branch = imm
@ -243,10 +252,12 @@ module serv_decode
o_sh_right = co_sh_right;
o_bne_or_bge = co_bne_or_bge;
o_cond_branch = co_cond_branch;
o_dbus_en = co_dbus_en;
o_mtval_pc = co_mtval_pc;
o_two_stage_op = co_two_stage_op;
o_e_op = co_e_op;
o_ebreak = co_ebreak;
o_branch_op = co_branch_op;
o_mem_op = co_mem_op;
o_shift_op = co_shift_op;
o_slt_op = co_slt_op;
o_rd_op = co_rd_op;
@ -282,6 +293,7 @@ module serv_decode
o_op_b_source = co_op_b_source;
o_rd_csr_en = co_rd_csr_en;
o_rd_alu_en = co_rd_alu_en;
o_rd_mem_en = co_rd_mem_en;
end
end else begin
@ -304,8 +316,10 @@ module serv_decode
o_cond_branch <= co_cond_branch;
o_e_op <= co_e_op;
o_ebreak <= co_ebreak;
o_two_stage_op <= co_two_stage_op;
o_dbus_en <= co_dbus_en;
o_mtval_pc <= co_mtval_pc;
o_branch_op <= co_branch_op;
o_mem_op <= co_mem_op;
o_shift_op <= co_shift_op;
o_slt_op <= co_slt_op;
o_rd_op <= co_rd_op;
@ -341,6 +355,7 @@ module serv_decode
o_op_b_source <= co_op_b_source;
o_rd_csr_en <= co_rd_csr_en;
o_rd_alu_en <= co_rd_alu_en;
o_rd_mem_en <= co_rd_mem_en;
end
end

3
rtl/serv_mem_if.v
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@ -14,7 +14,6 @@ module serv_mem_if
output wire o_sh_done,
output wire o_sh_done_r,
//Control
input wire i_mem_op,
input wire i_shift_op,
input wire i_signed,
input wire i_word,
@ -61,7 +60,7 @@ module serv_mem_if
(i_bytecnt == 2'b00) |
(i_half & !i_bytecnt[1]);
assign o_rd = (i_mem_op | i_mdu_op) & ((dat_valid|i_mdu_op) ? dat_cur : signbit & i_signed);
assign o_rd = (dat_valid|i_mdu_op) ? dat_cur : signbit & i_signed;
assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;

7
rtl/serv_rf_if.v
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@ -18,7 +18,7 @@ module serv_rf_if
input wire i_trap,
input wire i_mret,
input wire i_mepc,
input wire i_mem_op,
input wire i_mtval_pc,
input wire i_bufreg_q,
input wire i_bad_pc,
output wire o_csr_pc,
@ -36,6 +36,7 @@ module serv_rf_if
input wire i_csr_rd,
input wire i_rd_csr_en,
input wire i_mem_rd,
input wire i_rd_mem_en,
//RS1 read port
input wire [4:0] i_rs1_raddr,
@ -56,9 +57,9 @@ module serv_rf_if
wire rd = (i_ctrl_rd ) |
(i_alu_rd & i_rd_alu_en) |
(i_csr_rd & i_rd_csr_en) |
(i_mem_rd);
(i_mem_rd & i_rd_mem_en);
wire mtval = i_mem_op ? i_bufreg_q : i_bad_pc;
wire mtval = i_mtval_pc ? i_bad_pc : i_bufreg_q;
assign o_wdata0 = i_trap ? mtval : rd;
assign o_wdata1 = i_trap ? i_mepc : i_csr;

15
rtl/serv_state.v
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@ -30,8 +30,9 @@ module serv_state
//Control
input wire i_bne_or_bge,
input wire i_cond_branch,
input wire i_dbus_en,
input wire i_two_stage_op,
input wire i_branch_op,
input wire i_mem_op,
input wire i_shift_op,
input wire i_sh_right,
input wire i_slt_op,
@ -56,7 +57,6 @@ module serv_state
reg stage_two_req;
reg init_done;
wire misalign_trap_sync;
wire two_stage_op;
reg [4:2] o_cnt;
reg [3:0] o_cnt_r;
@ -85,9 +85,6 @@ module serv_state
//been calculated.
wire take_branch = i_branch_op & (!i_cond_branch | (i_alu_cmp^i_bne_or_bge));
//slt*, branch/jump, shift, load/store, (optionally mdu ops)
assign two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op | (MDU & i_mdu_op);
//valid signal for mdu
assign o_mdu_valid = MDU & !o_cnt_en & init_done & i_mdu_op;
@ -95,10 +92,10 @@ module serv_state
// and the first stage didn't cause a misalign exception
assign o_rf_wreq = !misalign_trap_sync &
((i_shift_op & (i_sh_done | !i_sh_right) & !o_cnt_en & init_done) |
(i_mem_op & i_dbus_ack) | (MDU & i_mdu_ready) |
i_dbus_ack | (MDU & i_mdu_ready) |
(stage_two_req & (i_slt_op | i_branch_op)));
assign o_dbus_cyc = !o_cnt_en & init_done & i_mem_op & !i_mem_misalign;
assign o_dbus_cyc = !o_cnt_en & init_done & i_dbus_en & !i_mem_misalign;
//Prepare RF for reads when a new instruction is fetched
// or when stage one caused an exception (rreq implies a write request too)
@ -121,7 +118,7 @@ module serv_state
assign o_ibus_cyc = ibus_cyc & !i_rst;
assign o_init = two_stage_op & !i_new_irq & !init_done;
assign o_init = i_two_stage_op & !i_new_irq & !init_done;
always @(posedge i_clk) begin
//ibus_cyc changes on three conditions.
@ -190,7 +187,7 @@ module serv_state
//trap_pending is only guaranteed to have correct value during the
// last cycle of the init stage
wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign) |
(i_mem_op & i_mem_misalign));
(i_dbus_en & i_mem_misalign));
always @(posedge i_clk) begin
if (o_cnt_done)

22
rtl/serv_top.v
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@ -78,10 +78,10 @@ module serv_top
wire sh_right;
wire bne_or_bge;
wire cond_branch;
wire two_stage_op;
wire e_op;
wire ebreak;
wire branch_op;
wire mem_op;
wire shift_op;
wire slt_op;
wire rd_op;
@ -89,10 +89,12 @@ module serv_top
wire rd_alu_en;
wire rd_csr_en;
wire rd_mem_en;
wire ctrl_rd;
wire alu_rd;
wire mem_rd;
wire csr_rd;
wire mtval_pc;
wire ctrl_pc_en;
wire jump;
@ -160,6 +162,7 @@ module serv_top
wire csr_imm_en;
wire csr_in;
wire rf_csr_out;
wire dbus_en;
wire new_irq;
@ -200,8 +203,9 @@ module serv_top
//Control
.i_bne_or_bge (bne_or_bge),
.i_cond_branch (cond_branch),
.i_dbus_en (dbus_en),
.i_two_stage_op (two_stage_op),
.i_branch_op (branch_op),
.i_mem_op (mem_op),
.i_shift_op (shift_op),
.i_sh_right (sh_right),
.i_slt_op (slt_op),
@ -235,15 +239,16 @@ module serv_top
//To state
.o_bne_or_bge (bne_or_bge),
.o_cond_branch (cond_branch),
.o_dbus_en (dbus_en),
.o_e_op (e_op),
.o_ebreak (ebreak),
.o_branch_op (branch_op),
.o_mem_op (mem_op),
.o_shift_op (shift_op),
.o_slt_op (slt_op),
.o_rd_op (rd_op),
.o_sh_right (sh_right),
.o_mdu_op (mdu_op),
.o_two_stage_op (two_stage_op),
//Extension
.o_ext_funct3 (o_ext_funct3),
@ -278,9 +283,12 @@ module serv_top
.o_csr_source (csr_source),
.o_csr_d_sel (csr_d_sel),
.o_csr_imm_en (csr_imm_en),
.o_mtval_pc (mtval_pc ),
//To top
.o_immdec_ctrl (immdec_ctrl),
.o_immdec_en (immdec_en),
//To RF IF
.o_rd_mem_en (rd_mem_en),
.o_rd_csr_en (rd_csr_en),
.o_rd_alu_en (rd_alu_en));
@ -396,7 +404,7 @@ module serv_top
.i_trap (trap),
.i_mret (mret),
.i_mepc (o_ibus_adr[0]),
.i_mem_op (mem_op),
.i_mtval_pc (mtval_pc),
.i_bufreg_q (bufreg_q),
.i_bad_pc (bad_pc),
.o_csr_pc (csr_pc),
@ -413,6 +421,7 @@ module serv_top
.i_csr_rd (csr_rd),
.i_rd_csr_en (rd_csr_en),
.i_mem_rd (mem_rd),
.i_rd_mem_en (rd_mem_en),
//RS1 read port
.i_rs1_raddr (rs1_addr),
@ -441,7 +450,6 @@ module serv_top
.o_sh_done_r (mem_sh_done_r),
//Control
.i_mdu_op (mdu_op),
.i_mem_op (mem_op),
.i_shift_op (shift_op),
.i_signed (mem_signed),
.i_word (mem_word),
@ -470,7 +478,7 @@ module serv_top
.i_cnt3 (cnt3),
.i_cnt7 (cnt7),
.i_cnt_done (cnt_done),
.i_mem_op (mem_op),
.i_mem_op (!mtval_pc),
.i_mtip (i_timer_irq),
.i_trap (trap),
.o_new_irq (new_irq),
@ -501,7 +509,7 @@ module serv_top
`ifdef RISCV_FORMAL
reg [31:0] pc = RESET_PC;
wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en;
wire rs_en = two_stage_op ? init : ctrl_pc_en;
always @(posedge clk) begin
/* End of instruction */