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Use bufreg for shifter
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Olof Kindgren
parent
102936ba40
commit
a550137453
@ -5,40 +5,27 @@ module ser_shift
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input wire i_rst,
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input wire i_load,
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input wire [4:0] i_shamt,
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input wire i_signed,
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input wire i_shamt_msb,
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input wire i_signbit,
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input wire i_right,
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output wire o_done,
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input wire i_d,
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output wire o_q);
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wire [31:0] shiftreg;
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reg signbit = 1'b0;
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reg wrapped = 1'b0;
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reg [4:0] cnt = 5'd0;
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shift_reg #(.LEN (32)) sh_reg
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(.clk (i_clk),
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.i_rst (i_rst),
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.i_en (i_load),
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.i_d (i_d),
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.o_q (shiftreg[0]),
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.o_par (shiftreg[31:1]));
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reg signbit;
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reg [5:0] cnt;
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reg wrapped;
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always @(posedge i_clk) begin
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cnt <= cnt + 5'd1;
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if (cnt == 31) begin
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signbit <= shiftreg[cnt];
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wrapped <= 1'b1;
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end
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cnt <= cnt + 6'd1;
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if (i_load) begin
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cnt <= i_shamt;
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wrapped <= 1'b0;
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cnt <= 6'd0;
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signbit <= i_signbit & i_right;
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end
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wrapped <= cnt[5] | (i_shamt_msb & !i_right);
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end
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wire shiftreg_valid = (i_shamt == 0) | (wrapped^i_right);
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assign o_q = shiftreg_valid ? shiftreg[cnt] : signbit & i_signed;
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assign o_done = (cnt == i_shamt);
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assign o_q = (i_right^wrapped) ? i_d : signbit;
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endmodule
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@ -6,6 +6,7 @@ module serv_alu
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input wire i_en,
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input wire i_rs1,
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input wire i_op_b,
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input wire i_buf,
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input wire i_init,
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input wire i_cnt_done,
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input wire i_sub,
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@ -17,6 +18,7 @@ module serv_alu
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input wire i_shamt_en,
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input wire i_sh_right,
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input wire i_sh_signed,
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output wire o_sh_done,
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input wire [1:0] i_rd_sel,
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output wire o_rd);
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@ -30,6 +32,7 @@ module serv_alu
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reg result_lt_r;
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wire [4:0] shamt;
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reg shamt_msb;
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reg en_r;
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wire v;
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@ -54,11 +57,18 @@ module serv_alu
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.i_rst (i_rst),
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.i_load (i_init),
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.i_shamt (shamt),
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.i_signed (i_sh_signed),
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.i_shamt_msb (shamt_msb),
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.i_signbit (i_sh_signed & i_rs1),
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.i_right (i_sh_right),
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.i_d (i_rs1),
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.o_done (o_sh_done),
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.i_d (i_buf),
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.o_q (result_sh));
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wire b_inv_plus_1_cy;
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always @(posedge clk)
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if (i_shamt_en)
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shamt_msb <= b_inv_plus_1_cy;
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ser_add ser_add_inv_plus_1
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(
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@ -68,7 +78,7 @@ module serv_alu
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.b (plus_1),
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.clr (!i_en),
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.q (b_inv_plus_1),
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.o_v ());
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.o_v (b_inv_plus_1_cy));
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wire add_b = i_sub ? b_inv_plus_1 : i_op_b;
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@ -6,6 +6,7 @@ module serv_bufreg
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input wire [3:0] i_cnt_r,
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input wire i_en,
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input wire i_clr,
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input wire i_loop,
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input wire i_rs1,
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input wire i_rs1_en,
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input wire i_imm,
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@ -26,7 +27,7 @@ module serv_bufreg
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if (i_rst)
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data <= 32'd0;
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else if (i_en)
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data <= {q, data[31:1]};
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data <= {i_loop ? o_q : q, data[31:1]};
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if ((i_cnt[4:2] == 3'd0) & i_cnt_r[0] & i_en)
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o_lsb[0] <= q;
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@ -11,6 +11,9 @@ module serv_decode
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output wire [4:0] o_cnt,
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output reg [3:0] o_cnt_r,
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output wire o_cnt_done,
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output reg o_bufreg_hold,
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output wire o_bufreg_imm_en,
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output wire o_bufreg_loop,
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output wire o_ctrl_en,
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output wire o_ctrl_pc_en,
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output reg o_ctrl_jump,
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@ -21,6 +24,7 @@ module serv_decode
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output wire o_ctrl_trap,
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output wire o_ctrl_mret,
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input wire i_ctrl_misalign,
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output wire o_rf_rs_en,
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output wire o_rf_rd_en,
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output reg [4:0] o_rf_rd_addr,
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output reg [4:0] o_rf_rs1_addr,
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@ -36,6 +40,7 @@ module serv_decode
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output wire o_alu_shamt_en,
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output wire o_alu_sh_signed,
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output wire o_alu_sh_right,
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input wire i_alu_sh_done,
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output reg [1:0] o_alu_rd_sel,
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output wire o_mem_en,
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output wire o_mem_cmd,
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@ -104,6 +109,9 @@ module serv_decode
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assign e_op = (opcode[4:2] == 3'b111) & !op21 & !(|o_funct3);
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assign o_bufreg_imm_en = !opcode[2];
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assign o_bufreg_loop = op_or_opimm & !(state == INIT);
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assign o_ctrl_pc_en = running | o_ctrl_trap;
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wire take_branch = (opcode[4:2] == 3'b110) & (opcode[0] | i_alu_cmp);
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@ -273,6 +281,8 @@ module serv_decode
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o_csr_mcause <= {!op20,3'b011};
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end
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assign o_rf_rs_en = two_stage_op ? (state == INIT) : o_ctrl_pc_en;
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//slt*, branch/jump, shift, load/store
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wire two_stage_op =
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slt_op | (opcode[4:2] == 3'b110) | (opcode[2:1] == 2'b00) |
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@ -295,6 +305,8 @@ module serv_decode
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cnt_done <= (cnt[4:2] == 3'b111) & o_cnt_r[2];
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o_bufreg_hold <= 1'b0;
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case (state)
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IDLE : begin
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if (i_rf_ready) begin
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@ -303,14 +315,21 @@ module serv_decode
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state <= INIT;
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if (e_op | pending_irq)
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state <= TRAP;
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end
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end else if (i_alu_sh_done & shift_op & stage_one_done)
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state <= RUN;
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end
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INIT : begin
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stage_one_done <= 1'b1;
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if (cnt_done)
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state <= (i_mem_misalign | (take_branch & i_ctrl_misalign)) ? TRAP :
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mem_op ? IDLE : RUN;
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if (i_mem_misalign | (take_branch & i_ctrl_misalign))
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state <= TRAP;
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else if (mem_op | shift_op ) begin
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state <= IDLE;
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o_bufreg_hold <= 1'b1;
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end
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else
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state <= RUN;
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end
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RUN : begin
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stage_one_done <= 1'b0;
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@ -60,7 +60,7 @@ module serv_mem_if
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assign o_wb_sel[0] = (bytepos == 2'b00);
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assign o_wb_we = i_cmd;
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wire [1:0] bytepos;
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reg [1:0] bytepos;
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wire wbyte0 = (i_bytecnt == 2'b00);
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@ -77,9 +77,10 @@ module serv_mem_if
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wire [1:0] dat_sel = i_bytecnt[1] ? i_bytecnt : (i_bytecnt | bytepos);
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assign bytepos = i_lsb;
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always @(posedge i_clk) begin
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if (i_init)
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bytepos <= i_lsb;
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if (dat0_en)
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dat0 <= {i_rs2, dat0[7:1]};
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if (dat1_en)
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@ -76,6 +76,10 @@ module serv_top
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wire cnt_done;
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wire [2:0] funct3;
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wire bufreg_hold;
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wire bufreg_imm_en;
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wire bufreg_loop;
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wire alu_en;
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wire alu_init;
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wire alu_sub;
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@ -87,11 +91,13 @@ module serv_top
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wire alu_shamt_en;
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wire alu_sh_signed;
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wire alu_sh_right;
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wire alu_sh_done;
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wire [1:0] alu_rd_sel;
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wire rf_ready;
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wire rs1;
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wire rs2;
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wire rs_en;
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wire rd_en;
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wire op_b_source;
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@ -136,10 +142,13 @@ module serv_top
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.i_timer_irq_en (timer_irq_en),
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.i_wb_rdt (i_ibus_rdt),
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.i_wb_en (o_ibus_cyc & i_ibus_ack),
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.i_rf_ready (rf_ready),
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.i_rf_ready (rf_ready | i_dbus_ack),
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.o_cnt (cnt),
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.o_cnt_r (cnt_r),
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.o_cnt_done (cnt_done),
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.o_bufreg_hold (bufreg_hold),
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.o_bufreg_imm_en (bufreg_imm_en),
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.o_bufreg_loop (bufreg_loop),
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.o_ctrl_en (ctrl_en),
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.o_ctrl_pc_en (ctrl_pc_en),
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.o_ctrl_jump (jump),
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@ -162,7 +171,9 @@ module serv_top
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.o_alu_shamt_en (alu_shamt_en),
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.o_alu_sh_signed (alu_sh_signed),
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.o_alu_sh_right (alu_sh_right),
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.i_alu_sh_done (alu_sh_done),
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.o_alu_rd_sel (alu_rd_sel),
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.o_rf_rs_en (rs_en),
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.o_rf_rd_en (rd_en),
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.o_rf_rd_addr (rd_addr),
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.o_rf_rs1_addr (rs1_addr),
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@ -199,12 +210,13 @@ module serv_top
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.i_rst (i_rst),
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.i_cnt (cnt),
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.i_cnt_r (cnt_r),
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.i_en (alu_en),
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.i_en (!(bufreg_hold | o_dbus_cyc)),
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.i_clr (!mem_en),
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.i_loop (bufreg_loop),
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.i_rs1 (rs1),
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.i_rs1_en (1'b1),
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.i_imm (imm),
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.i_imm_en (1'b1),
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.i_imm_en (bufreg_imm_en),
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.o_lsb (lsb),
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.o_reg (bufreg_out),
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.o_q (bad_adr));
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@ -250,6 +262,7 @@ module serv_top
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.i_en (alu_en),
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.i_rs1 (rs1),
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.i_op_b (op_b),
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.i_buf (bad_adr), //FIXME
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.i_init (alu_init),
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.i_cnt_done (cnt_done),
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.i_sub (alu_sub),
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@ -261,6 +274,7 @@ module serv_top
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.i_shamt_en (alu_shamt_en),
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.i_sh_right (alu_sh_right),
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.i_sh_signed (alu_sh_signed),
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.o_sh_done (alu_sh_done),
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.i_rd_sel (alu_rd_sel),
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.o_rd (alu_rd));
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@ -268,7 +282,7 @@ module serv_top
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(
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.i_clk (clk),
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.i_rst (i_rst),
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.i_go (i_ibus_ack | i_dbus_ack),
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.i_go (i_ibus_ack),
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.o_ready (rf_ready),
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.i_rd_en (rd_en),
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.i_rd_addr (rd_addr),
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@ -345,7 +359,7 @@ module serv_top
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rvfi_insn <= i_ibus_rdt;
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ctrl_pc_en_r <= ctrl_pc_en;
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if (alu_en) begin
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if (rs_en) begin
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rs1_fv <= {rs1,rs1_fv[31:1]};
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rs2_fv <= {rs2,rs2_fv[31:1]};
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end
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