Further optimizations

rtl/riscv_timer.v

@@ -1,14 +1,15 @@
 `default_nettype none
 module riscv_timer
   (input wire 	     i_clk,
+   input wire 	      i_rst,
    output reg 	      o_irq = 1'b0,
    input wire [31:0]  i_wb_dat,
    input wire 	      i_wb_we,
    input wire 	      i_wb_cyc,
    output wire [31:0] o_wb_dat);
 
-   reg [31:0] 	     mtime = 32'd0;
-   reg [31:0] 	     mtimecmp = 32'd0;
+   reg [15:0] 	     mtime;
+   reg [15:0] 	     mtimecmp;
 
    assign o_wb_dat = mtime;
 
@@ -17,5 +18,9 @@ module riscv_timer
 	mtimecmp <= i_wb_dat;
       mtime <= mtime + 32'd1;
       o_irq <= (mtime >= mtimecmp);
+      if (i_rst) begin
+	 mtime <= 16'd0;
+	 mtimecmp <= 16'd0;
+      end
    end
 endmodule