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Add serv_csr block diagram

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Olof Kindgren 2020-08-25 19:04:45 +02:00
parent 915cdf7933
commit b405c5b78a
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doc/index.rst
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@ -70,6 +70,8 @@ serv_csr
serv_csr handles CSR accesses and all status related to (timer) interrupts. Out of the eight CSRs supported by SERV, only four resides in serv_csr (mstatus, mie, mcause and mip) and for those registers, SERV only implement the bits required for ecall, ebreak, misalignment and timer interrupts. The four remaining CSRs are commonly stored in the RF
.. image:: serv_csr_int.png
serv_ctrl
^^^^^^^^^

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