Fix width mismatches to make code verilator clean

bench/serv_mux.v

@@ -59,8 +59,8 @@ module serv_mux
 
    generate
       if (sim) begin
-	 wire sig_en = (i_wb_cpu_adr[31:28] == 8'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
-	 wire halt_en = (i_wb_cpu_adr[31:28] == 8'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
+	 wire sig_en = (i_wb_cpu_adr[31:28] == 4'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
+	 wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
 
 	 reg [1023:0] signature_file;
 	 integer      f = 0;

bench/serv_wrapper.v

@@ -159,6 +159,28 @@ serv_arbiter serv_arbiter
       .clk      (wb_clk),
       .i_rst    (wb_rst),
       .i_timer_irq  (timer_irq),
+`ifdef RISCV_FORMAL
+      .rvfi_valid     (),
+      .rvfi_order     (),
+      .rvfi_insn      (),
+      .rvfi_trap      (),
+      .rvfi_halt      (),
+      .rvfi_intr      (),
+      .rvfi_mode      (),
+      .rvfi_rs1_addr  (),
+      .rvfi_rs2_addr  (),
+      .rvfi_rs1_rdata (),
+      .rvfi_rs2_rdata (),
+      .rvfi_rd_addr   (),
+      .rvfi_rd_wdata  (),
+      .rvfi_pc_rdata  (),
+      .rvfi_pc_wdata  (),
+      .rvfi_mem_addr  (),
+      .rvfi_mem_rmask (),
+      .rvfi_mem_wmask (),
+      .rvfi_mem_rdata (),
+      .rvfi_mem_wdata (),
+`endif
 
       .o_ibus_adr   (wb_cpu_ibus_adr),
       .o_ibus_cyc   (wb_cpu_ibus_cyc),

rtl/riscv_timer.v

@@ -11,11 +11,11 @@ module riscv_timer
    reg [15:0] 	     mtime;
    reg [15:0] 	     mtimecmp;
 
-   assign o_wb_dat = mtime;
+   assign o_wb_dat = {16'd0,mtime};
 
    always @(posedge i_clk) begin
       if (i_wb_cyc & i_wb_we)
-	mtimecmp <= i_wb_dat;
+	mtimecmp <= i_wb_dat[15:0];
       mtime <= mtime + 16'd1;
       o_irq <= (mtime >= mtimecmp);
       if (i_rst) begin

rtl/ser_shift.v

@@ -15,7 +15,7 @@ module ser_shift
    reg 		    signbit;
    reg [5:0] 	    cnt;
    reg 		    wrapped;
-   
+
    always @(posedge i_clk) begin
       cnt <= cnt + 6'd1;
       if (i_load) begin
@@ -25,7 +25,7 @@ module ser_shift
       wrapped <= cnt[5] | (i_shamt_msb & !i_right);
    end
 
-   assign o_done = (cnt == i_shamt);
+   assign o_done = (cnt[4:0] == i_shamt);
    assign o_q = (i_right^wrapped) ? i_d : signbit;
 
 endmodule

rtl/serv_alu.v

@@ -18,7 +18,7 @@ module serv_alu
    input wire 	    i_shamt_en,
    input wire 	    i_sh_right,
    input wire 	    i_sh_signed,
-   output wire 	    o_sh_done, 
+   output wire 	    o_sh_done,
    input wire [1:0] i_rd_sel,
    output wire 	    o_rd);
 
@@ -63,7 +63,7 @@ module serv_alu
       .o_q (result_sh));
 
    wire        b_inv_plus_1_cy;
-        
+
    always @(posedge clk)
      if (i_shamt_en)
        shamt_msb <= b_inv_plus_1_cy;

rtl/serv_bufreg.v

@@ -19,7 +19,7 @@ module serv_bufreg
    reg 		      c_r;
    reg [31:0] 	      data;
 
-   assign {c,q} = (i_rs1 & i_rs1_en) + (i_imm & i_imm_en) + c_r;
+   assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en)} + c_r;
 
    always @(posedge i_clk) begin
       c_r <= c & !i_clr;

rtl/serv_clock_gen.v

@@ -5,7 +5,7 @@ module serv_clock_gen
    output wire o_clk,
    output wire o_rst);
 
-   parameter PLL = "NONE";
+   parameter [79:0] PLL = "NONE";
 
    generate
       if ((PLL == "ICE40_CORE") || (PLL == "ICE40_PAD")) begin

serv.core

@@ -119,7 +119,7 @@ targets:
     parameters : [RISCV_FORMAL, firmware, memsize, signature, uart_baudrate, vcd]
     tools:
       verilator:
-        verilator_options : [-Wno-fatal, --trace]
+        verilator_options : [--trace]
     toplevel : serv_wrapper
 
 parameters: