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Fix width mismatches to make code verilator clean

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Olof Kindgren
2019-03-25 15:39:18 +01:00
parent 3438e0f172
commit bba836ad8c
8 changed files with 33 additions and 11 deletions
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4
rtl/riscv_timer.v
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@@ -11,11 +11,11 @@ module riscv_timer
reg [15:0] mtime;
reg [15:0] mtimecmp;
assign o_wb_dat = mtime;
assign o_wb_dat = {16'd0,mtime};
always @(posedge i_clk) begin
if (i_wb_cyc & i_wb_we)
mtimecmp <= i_wb_dat;
mtimecmp <= i_wb_dat[15:0];
mtime <= mtime + 16'd1;
o_irq <= (mtime >= mtimecmp);
if (i_rst) begin