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Fix width mismatches to make code verilator clean

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Olof Kindgren
2019-03-25 15:39:18 +01:00
parent 3438e0f172
commit bba836ad8c
8 changed files with 33 additions and 11 deletions
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rtl/serv_bufreg.v
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@@ -19,7 +19,7 @@ module serv_bufreg
reg c_r;
reg [31:0] data;
assign {c,q} = (i_rs1 & i_rs1_en) + (i_imm & i_imm_en) + c_r;
assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en)} + c_r;
always @(posedge i_clk) begin
c_r <= c & !i_clr;