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Fix width mismatches to make code verilator clean

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Olof Kindgren
2019-03-25 15:39:18 +01:00
parent 3438e0f172
commit bba836ad8c
8 changed files with 33 additions and 11 deletions
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serv.core
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@@ -119,7 +119,7 @@ targets:
parameters : [RISCV_FORMAL, firmware, memsize, signature, uart_baudrate, vcd]
tools:
verilator:
verilator_options : [-Wno-fatal, --trace]
verilator_options : [--trace]
toplevel : serv_wrapper
parameters: