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Used named generate statements

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Unnamed generate statements are not recommended and some tools throw
warnings or errors for these.
This commit is contained in:
Olof Kindgren
2023-11-16 14:34:25 +01:00
parent 7a6d5d3fc9
commit bc74a9a1d7
8 changed files with 55 additions and 47 deletions
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4
rtl/serv_alu.v
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@@ -60,7 +60,9 @@ module serv_alu
assign result_slt[0] = cmp_r & i_cnt0; assign result_slt[0] = cmp_r & i_cnt0;
generate generate
if (W>1) assign result_slt[B:1] = {B{1'b0}}; if (W>1) begin : gen_w_gt_1
assign result_slt[B:1] = {B{1'b0}};
end
endgenerate endgenerate
assign o_rd = i_buf | assign o_rd = i_buf |

9
rtl/serv_ctrl.v
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@@ -53,10 +53,11 @@ module serv_ctrl
assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r; assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
generate generate
if (|WITH_CSR) if (|WITH_CSR) begin : gen_csr
assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4; assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
else end else begin : gen_no_csr
assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4; assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;
end
endgenerate endgenerate
assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr);

6
rtl/serv_decode.v
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@@ -82,7 +82,7 @@ module serv_decode
wire co_slt_or_branch = (opcode[4] | (funct3[1] & opcode[2]) | (imm30 & opcode[2] & opcode[3] & ~funct3[2])) & !co_mdu_op; wire co_slt_or_branch = (opcode[4] | (funct3[1] & opcode[2]) | (imm30 & opcode[2] & opcode[3] & ~funct3[2])) & !co_mdu_op;
wire co_branch_op = opcode[4]; wire co_branch_op = opcode[4];
wire co_dbus_en = ~opcode[2] & ~opcode[4]; wire co_dbus_en = ~opcode[2] & ~opcode[4];
wire co_mtval_pc = opcode[4]; wire co_mtval_pc = opcode[4];
wire co_mem_word = funct3[1]; wire co_mem_word = funct3[1];
wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op; wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
wire co_rd_mem_en = (!opcode[2] & !opcode[0]) | co_mdu_op; wire co_rd_mem_en = (!opcode[2] & !opcode[0]) | co_mdu_op;
@@ -233,7 +233,7 @@ module serv_decode
wire co_op_b_source = opcode[3]; wire co_op_b_source = opcode[3];
generate generate
if (PRE_REGISTER) begin if (PRE_REGISTER) begin : gen_pre_register
always @(posedge clk) begin always @(posedge clk) begin
if (i_wb_en) begin if (i_wb_en) begin
@@ -296,7 +296,7 @@ module serv_decode
o_rd_mem_en = co_rd_mem_en; o_rd_mem_en = co_rd_mem_en;
end end
end else begin end else begin : gen_post_register
always @(*) begin always @(*) begin
funct3 = i_wb_rdt[14:12]; funct3 = i_wb_rdt[14:12];

6
rtl/serv_immdec.v
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@@ -33,7 +33,7 @@ module serv_immdec
wire signbit = imm31 & !i_csr_imm_en; wire signbit = imm31 & !i_csr_imm_en;
generate generate
if (SHARED_RFADDR_IMM_REGS) begin if (SHARED_RFADDR_IMM_REGS) begin : gen_shared_imm_regs
assign o_rs1_addr = imm19_12_20[8:4]; assign o_rs1_addr = imm19_12_20[8:4];
assign o_rs2_addr = imm24_20; assign o_rs2_addr = imm24_20;
assign o_rd_addr = imm11_7; assign o_rd_addr = imm11_7;
@@ -57,7 +57,7 @@ module serv_immdec
if (i_wb_en | (i_cnt_en & i_immdec_en[0])) if (i_wb_en | (i_cnt_en & i_immdec_en[0]))
imm11_7 <= i_wb_en ? i_wb_rdt[11:7] : {imm30_25[0], imm11_7[4:1]}; imm11_7 <= i_wb_en ? i_wb_rdt[11:7] : {imm30_25[0], imm11_7[4:1]};
end end
end else begin end else begin : gen_separate_imm_regs
reg [4:0] rd_addr; reg [4:0] rd_addr;
reg [4:0] rs1_addr; reg [4:0] rs1_addr;
reg [4:0] rs2_addr; reg [4:0] rs2_addr;
@@ -91,5 +91,5 @@ module serv_immdec
endgenerate endgenerate
assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0]; assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0];
endmodule endmodule

4
rtl/serv_rf_if.v
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@@ -53,7 +53,7 @@ module serv_rf_if
wire rd_wen = i_rd_wen & (|i_rd_waddr); wire rd_wen = i_rd_wen & (|i_rd_waddr);
generate generate
if (|WITH_CSR) begin if (|WITH_CSR) begin : gen_csr
wire rd = (i_ctrl_rd ) | wire rd = (i_ctrl_rd ) |
(i_alu_rd & i_rd_alu_en) | (i_alu_rd & i_rd_alu_en) |
(i_csr_rd & i_rd_csr_en) | (i_csr_rd & i_rd_csr_en) |
@@ -119,7 +119,7 @@ module serv_rf_if
assign o_csr = i_rdata1 & i_csr_en; assign o_csr = i_rdata1 & i_csr_en;
assign o_csr_pc = i_rdata1; assign o_csr_pc = i_rdata1;
end else begin end else begin : gen_no_csr
wire rd = (i_ctrl_rd ) | wire rd = (i_ctrl_rd ) |
(i_alu_rd & i_rd_alu_en) | (i_alu_rd & i_rd_alu_en) |
(i_mem_rd & i_rd_mem_en); (i_mem_rd & i_rd_mem_en);

48
rtl/serv_rf_ram_if.v
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@@ -62,9 +62,9 @@ module serv_rf_ram_if
assign wtrig0 = rtrig1; assign wtrig0 = rtrig1;
generate if (width == 2) begin generate if (width == 2) begin : gen_w_eq_2
assign wtrig1 = wcnt[0]; assign wtrig1 = wcnt[0];
end else begin end else begin : gen_w_neq_2
reg wtrig0_r; reg wtrig0_r;
always @(posedge i_clk) wtrig0_r <= wtrig0; always @(posedge i_clk) wtrig0_r <= wtrig0;
assign wtrig1 = wtrig0_r; assign wtrig1 = wtrig0_r;
@@ -76,10 +76,11 @@ module serv_rf_ram_if
wdata0_r; wdata0_r;
wire [raw-1:0] wreg = wtrig1 ? i_wreg1 : i_wreg0; wire [raw-1:0] wreg = wtrig1 ? i_wreg1 : i_wreg0;
generate if (width == 32) generate if (width == 32) begin : gen_w_eq_32
assign o_waddr = wreg; assign o_waddr = wreg;
else end else begin : gen_w_neq_32
assign o_waddr = {wreg, wcnt[4:l2w]}; assign o_waddr = {wreg, wcnt[4:l2w]};
end
endgenerate endgenerate
assign o_wen = (wtrig0 & wen0_r) | (wtrig1 & wen1_r); assign o_wen = (wtrig0 & wen0_r) | (wtrig1 & wen1_r);
@@ -105,10 +106,11 @@ module serv_rf_ram_if
wire rtrig0; wire rtrig0;
wire [raw-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0; wire [raw-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0;
generate if (width == 32) generate if (width == 32) begin : gen_rreg_eq_32
assign o_raddr = rreg; assign o_raddr = rreg;
else end else begin : gen_rreg_neq_32
assign o_raddr = {rreg, rcnt[4:l2w]}; assign o_raddr = {rreg, rcnt[4:l2w]};
end
endgenerate endgenerate
reg [width-1:0] rdata0; reg [width-1:0] rdata0;
@@ -121,22 +123,24 @@ module serv_rf_ram_if
assign rtrig0 = (rcnt[l2w-1:0] == 1); assign rtrig0 = (rcnt[l2w-1:0] == 1);
generate if (width == 2) generate if (width == 2) begin : gen_ren_w_eq_2
assign o_ren = rgate; assign o_ren = rgate;
else end else begin : gen_ren_w_neq_2
assign o_ren = rgate & (rcnt[l2w-1:1] == 0); assign o_ren = rgate & (rcnt[l2w-1:1] == 0);
end
endgenerate endgenerate
reg rreq_r; reg rreq_r;
generate if (width>2) generate if (width>2) begin : gen_rdata1_w_neq_2
always @(posedge i_clk) begin always @(posedge i_clk) begin
rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize?
if (rtrig1) if (rtrig1)
rdata1[width-2:0] <= i_rdata[width-1:1]; rdata1[width-2:0] <= i_rdata[width-1:1];
end end
else end else begin : gen_rdata1_w_eq_2
always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
end
endgenerate endgenerate
always @(posedge i_clk) begin always @(posedge i_clk) begin

7
rtl/serv_state.v
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@@ -204,7 +204,7 @@ module serv_state
assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync); assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync);
generate generate
if (WITH_CSR) begin if (WITH_CSR) begin : gen_csr
reg misalign_trap_sync_r; reg misalign_trap_sync_r;
//trap_pending is only guaranteed to have correct value during the //trap_pending is only guaranteed to have correct value during the
@@ -217,7 +217,8 @@ module serv_state
misalign_trap_sync_r <= !(i_ibus_ack | i_rst) & ((trap_pending & o_init) | misalign_trap_sync_r); misalign_trap_sync_r <= !(i_ibus_ack | i_rst) & ((trap_pending & o_init) | misalign_trap_sync_r);
end end
assign misalign_trap_sync = misalign_trap_sync_r; assign misalign_trap_sync = misalign_trap_sync_r;
end else end else begin : gen_no_csr
assign misalign_trap_sync = 1'b0; assign misalign_trap_sync = 1'b0;
end
endgenerate endgenerate
endmodule endmodule

18
rtl/serv_top.v
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@@ -182,7 +182,7 @@ module serv_top
wire wb_ibus_ack; wire wb_ibus_ack;
generate generate
if (ALIGN) begin if (ALIGN) begin : gen_align
serv_aligner align serv_aligner align
( (
.clk(clk), .clk(clk),
@@ -197,7 +197,7 @@ module serv_top
.o_wb_ibus_cyc(o_ibus_cyc), .o_wb_ibus_cyc(o_ibus_cyc),
.i_wb_ibus_rdt(i_ibus_rdt), .i_wb_ibus_rdt(i_ibus_rdt),
.i_wb_ibus_ack(i_ibus_ack)); .i_wb_ibus_ack(i_ibus_ack));
end else begin end else begin : gen_no_align
assign o_ibus_adr = wb_ibus_adr; assign o_ibus_adr = wb_ibus_adr;
assign o_ibus_cyc = wb_ibus_cyc; assign o_ibus_cyc = wb_ibus_cyc;
assign wb_ibus_rdt = i_ibus_rdt; assign wb_ibus_rdt = i_ibus_rdt;
@@ -205,8 +205,8 @@ module serv_top
end end
endgenerate endgenerate
generate generate
if (COMPRESSED) begin if (COMPRESSED) begin : gen_compressed
serv_compdec compdec serv_compdec compdec
( (
.i_clk(clk), .i_clk(clk),
@@ -214,7 +214,7 @@ module serv_top
.i_ack(wb_ibus_ack), .i_ack(wb_ibus_ack),
.o_instr(i_wb_rdt), .o_instr(i_wb_rdt),
.o_iscomp(iscomp)); .o_iscomp(iscomp));
end else begin end else begin : gen_no_compressed
assign i_wb_rdt = wb_ibus_rdt; assign i_wb_rdt = wb_ibus_rdt;
assign iscomp = 1'b0; assign iscomp = 1'b0;
end end
@@ -533,7 +533,7 @@ module serv_top
.o_wb_sel (o_dbus_sel)); .o_wb_sel (o_dbus_sel));
generate generate
if (|WITH_CSR) begin if (|WITH_CSR) begin : gen_csr
serv_csr serv_csr
#(.RESET_STRATEGY (RESET_STRATEGY)) #(.RESET_STRATEGY (RESET_STRATEGY))
csr csr
@@ -567,7 +567,7 @@ module serv_top
.i_csr_imm (csr_imm), .i_csr_imm (csr_imm),
.i_rs1 (rs1), .i_rs1 (rs1),
.o_q (csr_rd)); .o_q (csr_rd));
end else begin end else begin : gen_no_csr
assign csr_in = 1'b0; assign csr_in = 1'b0;
assign csr_rd = 1'b0; assign csr_rd = 1'b0;
assign new_irq = 1'b0; assign new_irq = 1'b0;
@@ -645,10 +645,10 @@ module serv_top
`endif `endif
generate generate
if (MDU) begin if (MDU) begin: gen_mdu
assign dbus_rdt = i_ext_ready ? i_ext_rd:i_dbus_rdt; assign dbus_rdt = i_ext_ready ? i_ext_rd:i_dbus_rdt;
assign dbus_ack = i_dbus_ack | i_ext_ready; assign dbus_ack = i_dbus_ack | i_ext_ready;
end else begin end else begin : gen_no_mdu
assign dbus_rdt = i_dbus_rdt; assign dbus_rdt = i_dbus_rdt;
assign dbus_ack = i_dbus_ack; assign dbus_ack = i_dbus_ack;
end end