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Make serv_alu.v synthesizable with Vivado

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Katherine Watson
2023-11-10 18:05:49 -08:00
committed by Olof Kindgren
parent c7fc57213c
commit 7a6d5d3fc9
1 changed files with 1 additions and 1 deletions
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rtl/serv_alu.v
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@@ -60,7 +60,7 @@ module serv_alu
assign result_slt[0] = cmp_r & i_cnt0;
generate
if (W>1) assign result_slt[B:1] = '0;
if (W>1) assign result_slt[B:1] = {B{1'b0}};
endgenerate
assign o_rd = i_buf |