Expose and document PRE_REGISTER

rtl/serv_decode.v

@@ -1,6 +1,6 @@
 `default_nettype none
 module serv_decode #(
-   parameter integer PRE_REGISTER = 1
+   parameter [0:0] PRE_REGISTER = 1
 )(
    input wire        clk,
    //Input

rtl/serv_rf_top.v

@@ -3,6 +3,11 @@
 module serv_rf_top
   #(parameter RESET_PC = 32'd0,
 
+    /* Register signals before or after the decoder
+       0 : Register after the decoder. Faster but uses more resources
+       1 : (default) Register before the decoder. Slower but uses less resources
+     */
+    parameter PRE_REGISTER = 1,
     /* Amount of reset applied to design
        "NONE" : No reset at all. Relies on a POR to set correct initialization
                  values and that core isn't reset during runtime
@@ -113,6 +118,7 @@ module serv_rf_top
 
    serv_top
      #(.RESET_PC (RESET_PC),
+       .PRE_REGISTER (PRE_REGISTER),
        .RESET_STRATEGY (RESET_STRATEGY),
        .WITH_CSR (WITH_CSR))
    cpu

rtl/serv_top.v

@@ -2,6 +2,7 @@
 
 module serv_top
   #(parameter WITH_CSR = 1,
+    parameter PRE_REGISTER = 1,
     parameter RESET_STRATEGY = "MINI",
     parameter RESET_PC = 32'd0)
    (
@@ -204,7 +205,9 @@ module serv_top
       .i_rf_ready     (i_rf_ready),
       .o_rf_rd_en     (rd_en));
 
-   serv_decode decode
+   serv_decode
+     #(.PRE_REGISTER (PRE_REGISTER))
+   decode
      (
       .clk (clk),
       //Input

serv.core

@@ -25,6 +25,7 @@ targets:
   default:
     filesets : [core]
     parameters :
+      - "is_toplevel? (PRE_REGISTER)"
       - "is_toplevel? (RESET_STRATEGY)"
       - RISCV_FORMAL
       - SERV_CLEAR_RAM
@@ -42,6 +43,11 @@ targets:
     toplevel : serv_rf_top
 
 parameters:
+  PRE_REGISTER:
+    datatype    : int
+    description : Register signals before or after the decoder
+    paramtype   : vlogparam
+
   RESET_STRATEGY:
     datatype : str
     paramtype : vlogparam