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Avoid releasing trap signal too early

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The trap signal is used my the mux in serv_rf_if to decide which
registers to write to. If the trap signal is dropped too early,
the destination address changes while the register is still being
written to.
This commit is contained in:
Olof Kindgren
2023-10-29 22:25:50 +01:00
parent 46a820ee42
commit c7fc57213c
3 changed files with 5 additions and 8 deletions
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4
rtl/serv_csr.v
View File

@@ -5,7 +5,7 @@ module serv_csr
input wire i_clk,
input wire i_rst,
//State
input wire i_init,
input wire i_trig_irq,
input wire i_en,
input wire i_cnt0to3,
input wire i_cnt3,
@@ -74,7 +74,7 @@ module serv_csr
assign o_csr_in = csr_in;
always @(posedge i_clk) begin
if (!i_init & i_cnt_done) begin
if (i_trig_irq) begin
timer_irq_r <= timer_irq;
o_new_irq <= timer_irq & !timer_irq_r;
end

7
rtl/serv_state.v
View File

@@ -213,11 +213,8 @@ module serv_state
(i_dbus_en & i_mem_misalign));
always @(posedge i_clk) begin
if (o_cnt_done)
misalign_trap_sync_r <= trap_pending & o_init;
if (i_rst)
if (RESET_STRATEGY != "NONE")
misalign_trap_sync_r <= 1'b0;
if (i_ibus_ack | o_cnt_done | i_rst)
misalign_trap_sync_r <= !(i_ibus_ack | i_rst) & ((trap_pending & o_init) | misalign_trap_sync_r);
end
assign misalign_trap_sync = misalign_trap_sync_r;
end else

2
rtl/serv_top.v
View File

@@ -541,7 +541,7 @@ module serv_top
.i_clk (clk),
.i_rst (i_rst),
//State
.i_init (init),
.i_trig_irq (wb_ibus_ack),
.i_en (cnt_en),
.i_cnt0to3 (cnt0to3),
.i_cnt3 (cnt3),