Refactor testbench

Introduce an intermediate common simulation toplevel for verilator
and other sims

bench/servant_sim.v

@@ -0,0 +1,25 @@
+`default_nettype none
+module servant_sim
+  (input wire  wb_clk,
+   input wire  wb_rst,
+   output wire q);
+
+   parameter memfile = "";
+   parameter memsize = 8192;
+   parameter with_csr = 1;
+
+   reg [1023:0] firmware_file;
+   initial
+     if ($value$plusargs("firmware=%s", firmware_file)) begin
+	$display("Loading RAM from %0s", firmware_file);
+	$readmemh(firmware_file, dut.ram.mem);
+     end
+
+   servant
+     #(.memfile  (memfile),
+       .memsize  (memsize),
+       .sim      (1),
+       .with_csr (with_csr))
+   dut(wb_clk, wb_rst, q);
+
+endmodule

bench/servant_tb.cpp

@@ -2,7 +2,7 @@
 #include <signal.h>
 
 #include "verilated_vcd_c.h"
-#include "Vservant.h"
+#include "Vservant_sim.h"
 
 using namespace std;
 
@@ -91,7 +91,7 @@ int main(int argc, char **argv, char **env)
 	uart_context_t uart_context;
 	Verilated::commandArgs(argc, argv);
 
-	Vservant* top = new Vservant;
+	Vservant_sim* top = new Vservant_sim;
 
 	const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
 	if (arg[0]) {

bench/servant_tb.v

@@ -2,24 +2,23 @@
 module servant_tb;
 
    parameter memfile = "";
+   parameter memsize = 8192;
+   parameter with_csr = 1;
 
    reg wb_clk = 1'b0;
    reg wb_rst = 1'b1;
 
-   reg q_r = 1'b0;
-   wire q;
-
    always  #31 wb_clk <= !wb_clk;
    initial #62 wb_rst <= 1'b0;
 
    vlog_tb_utils vtu();
 
-   servant #(memfile) dut(wb_clk, wb_rst, q);
+   uart_decoder #(57600) uart_decoder (q);
 
-   always @(posedge wb_clk)
-     if (q != q_r) begin
-	$display("%0t : q is %s", $time, q ? "ON" : "OFF");
-	q_r <= q;
-     end
+   servant_sim
+     #(.memfile  (memfile),
+       .memsize  (memsize),
+       .with_csr (with_csr))
+   dut(wb_clk, wb_rst, q);
 
 endmodule

bench/uart_decoder.v

@@ -0,0 +1,18 @@
+module uart_decoder
+  #(parameter BAUD_RATE = 115200)
+   (input rx);
+
+   localparam T = 1000000000/BAUD_RATE;
+
+   integer i;
+   reg [7:0] ch;
+
+   initial forever begin
+      @(negedge rx);
+      #(T/2) ch = 0;
+      for (i=0;i<8;i=i+1)
+	#T ch[i] = rx;
+      $write("%c",ch);
+      $fflush;
+   end
+endmodule

servant.core

@@ -15,7 +15,12 @@ filesets:
     file_type : user
 
   servant_tb:
-    files: [bench/servant_tb.v : {file_type : verilogSource}]
+    files:
+      - bench/servant_sim.v
+      - "!tool_verilator? (bench/uart_decoder.v)"
+      - "!tool_verilator? (bench/servant_tb.v)"
+      - "tool_verilator? (bench/servant_tb.cpp)" : {file_type : cppSource}
+    file_type : verilogSource
     depend : [vlog_tb_utils]
 
   soc:
@@ -40,7 +45,7 @@ filesets:
 
   tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
   icebreaker : {files: [data/icebreaker.pcf  : {file_type : PCF}]}
-  verilator_tb: {files: [bench/servant_tb.cpp : {file_type : cppSource}]}
+
   nexys_a7:
     files:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
@@ -115,12 +120,16 @@ targets:
   sim:
     default_tool: icarus
     filesets : [soc, servant_tb]
-    parameters : [RISCV_FORMAL=true, firmware]
+    parameters :
+      - RISCV_FORMAL
+      - SERV_CLEAR_RAM=true
+      - firmware
+      - memsize
     toplevel : servant_tb
 
   verilator_tb:
     default_tool: verilator
-    filesets : [soc, verilator_tb]
+    filesets : [soc, servant_tb]
     parameters :
       - RISCV_FORMAL
       - firmware
@@ -133,7 +142,7 @@ targets:
     tools:
       verilator:
         verilator_options : [--trace]
-    toplevel : servant
+    toplevel : servant_sim
 
 parameters:
   PLL:
@@ -145,6 +154,10 @@ parameters:
     datatype  : bool
     paramtype : vlogdefine
 
+  SERV_CLEAR_RAM:
+    datatype  : bool
+    paramtype : vlogdefine
+
   firmware:
     datatype : file
     description : Preload RAM with a hex file at runtime (overrides memfile)

servant/servant.v

@@ -7,6 +7,7 @@ module servant
 
    parameter memfile = "zephyr_hello.hex";
    parameter memsize = 8192;
+   parameter sim = 0;
    parameter with_csr = 1;
 
    wire 	timer_irq;
@@ -72,14 +73,8 @@ module servant
       .i_wb_cpu_rdt (wb_mem_rdt),
       .i_wb_cpu_ack (wb_mem_ack));
 
-
-`ifdef VERILATOR
-   parameter sim = 1;
-`else
-   parameter sim = 0;
-`endif
    servant_mux #(sim) servant_mux
-  (
+     (
       .i_clk (wb_clk),
       .i_rst (wb_rst),
       .i_wb_cpu_adr (wb_dbus_adr),
@@ -107,24 +102,8 @@ module servant
       .o_wb_timer_cyc (wb_timer_cyc),
       .i_wb_timer_rdt (wb_timer_rdt));
 
-`ifndef SYNTHESIS
-//synthesis translate_off
-   reg [1023:0] firmware_file;
-   initial
-     /* verilator lint_off WIDTH */
-     if ($value$plusargs("firmware=%s", firmware_file)) begin
-	$display("Loading RAM from %0s", firmware_file);
-	$readmemh(firmware_file, ram.mem);
-     end
-     /* verilator lint_on WIDTH */
-//synthesis translate_on
-`endif
-
    servant_ram
-     #(
-`ifndef VERILATOR
-.memfile (memfile),
-`endif
+     #(.memfile (memfile),
        .depth (memsize))
    ram
      (// Wishbone interface