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Refactor testbench

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Introduce an intermediate common simulation toplevel for verilator
and other sims
This commit is contained in:
Olof Kindgren
2020-03-03 09:15:50 +01:00
parent 3468958f1e
commit c9a3c883f1
6 changed files with 74 additions and 40 deletions
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4
bench/servant_tb.cpp
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@@ -2,7 +2,7 @@
#include <signal.h>
#include "verilated_vcd_c.h"
#include "Vservant.h"
#include "Vservant_sim.h"
using namespace std;
@@ -91,7 +91,7 @@ int main(int argc, char **argv, char **env)
uart_context_t uart_context;
Verilated::commandArgs(argc, argv);
Vservant* top = new Vservant;
Vservant_sim* top = new Vservant_sim;
const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
if (arg[0]) {