Interrupts working. Adding philosophers example

README.md

@@ -43,6 +43,11 @@ Build and run the single threaded zephyr hello world example with verilator
 
     fusesoc run	--target=verilator_tb serv --uart_baudrate=57600 --firmware=../serv/sw/zephyr_hello_mt.hex --memsize=16384
 
+...or... the philosophers example
+
+    fusesoc run	--target=verilator_tb serv --uart_baudrate=57600 --firmware=../serv/sw/zephyr_phil.hex --memsize=32768
+
+
 Other applications can be tested by compiling and converting to bin and then hex e.g. with makehex.py found in $SERV/serv/riscv-target/serv
 
 Run the compliance tests
@@ -85,6 +90,6 @@ Run with `--firmware=../serv/sw/blinky.hex` as the last argument to run the LED
 TODO
 ----
 
-- Interrupts don't seem to work.
 - Applications have to be preloaded to RAM at compile-time
 - Store bootloader and register file together in a RAM
+- Make it faster and smaller

rtl/riscv_timer.v

@@ -16,7 +16,7 @@ module riscv_timer
    always @(posedge i_clk) begin
       if (i_wb_cyc & i_wb_we)
 	mtimecmp <= i_wb_dat;
-      mtime <= mtime + 32'd1;
+      mtime <= mtime + 16'd1;
       o_irq <= (mtime >= mtimecmp);
       if (i_rst) begin
 	 mtime <= 16'd0;

rtl/serv_csr.v

@@ -55,7 +55,8 @@ module serv_csr
 		   (i_csr_source == CSR_SOURCE_CSR) ? csr_out :
 		   1'bx;
 
-   assign csr_out = (i_csr_sel == CSR_SEL_MTVEC)    ? mtvec[0]  :
+   assign csr_out = (i_csr_sel == CSR_SEL_MSTATUS) ? mstatus :
+		    (i_csr_sel == CSR_SEL_MTVEC)    ? mtvec[0]  :
 		    (i_csr_sel == CSR_SEL_MSCRATCH) ? mscratch[0]   :
 		    (i_csr_sel == CSR_SEL_MEPC)    ? mepc[0]   :
 		    (i_csr_sel == CSR_SEL_MCAUSE)  ? mcause[0] :
@@ -76,11 +77,12 @@ module serv_csr
 
       mstatus <= (i_cnt == 2) ? mstatus_mie : 1'b0;
       mie <= (i_cnt == 6) & mie_mtie;
-      mip <= (i_cnt == 6) & i_mtip;
-
-      if (i_trap)
-	mcause[3:0] <= i_mcause;
+      mip <= (i_cnt == 6) & i_mtip & o_timer_irq_en;
 
+      if (i_trap) begin
+	 mcause[31]  <= i_mtip & o_timer_irq_en;
+	 mcause[3:0] <= (i_mtip & o_timer_irq_en) ? 4'd7 : i_mcause[3:0];
+      end
       if (mscratch_en)
 	mscratch <= {csr_in, mscratch[31:1]};
 

rtl/serv_decode.v

@@ -4,6 +4,7 @@ module serv_decode
    input wire 	     clk,
    input wire 	     i_rst,
    input wire 	     i_mtip,
+   input wire 	     i_timer_irq_en,
    input wire [31:0] i_wb_rdt,
    input wire 	     i_wb_en,
    input wire 	     i_rf_ready,
@@ -289,15 +290,11 @@ module serv_decode
    assign o_ctrl_trap = (state == TRAP);
 
    always @(posedge clk) begin
-      if (i_mtip)
-	o_csr_mcause[3:0] <= 4'd7;
-      else begin
-	 o_csr_mcause[3:0] <= 4'd0;
-	 if (i_mem_misalign)
-	   o_csr_mcause[3:0] <= {2'b01, o_mem_cmd, 1'b0};
-	 if (e_op)
-	   o_csr_mcause <= {!op[20],3'b011};
-      end
+      o_csr_mcause[3:0] <= 4'd0;
+      if (i_mem_misalign)
+	o_csr_mcause[3:0] <= {2'b01, o_mem_cmd, 1'b0};
+      if (e_op)
+	o_csr_mcause <= {!op[20],3'b011};
    end
 
    wire two_stage_op =
@@ -305,7 +302,15 @@ module serv_decode
         shift_op;
    reg 	stage_one_done;
 
+   reg 	mtip_r;
+   reg 	pending_irq;
+
    always @(posedge clk) begin
+      mtip_r <= i_mtip;
+
+      if (i_mtip & !mtip_r & i_timer_irq_en)
+	pending_irq <= 1'b1;
+
       cnt_done <= cnt == 30;
 
       case (state)
@@ -314,7 +319,7 @@ module serv_decode
 	      state <= RUN;
               if (two_stage_op & !stage_one_done)
 		state <= INIT;
-	      if (e_op | i_mtip)
+	      if (e_op | pending_irq)
 		state <= TRAP;
 	   end
         end
@@ -331,6 +336,7 @@ module serv_decode
              state <= IDLE;
         end
 	TRAP : begin
+	   pending_irq <= 1'b0;
            if (cnt_done)
              state <= IDLE;
 	end

rtl/serv_top.v

@@ -120,13 +120,13 @@ module serv_top
    wire 	 lui;
 
    wire 	 timer_irq_en;
-   wire 	 timer_irq = i_timer_irq & timer_irq_en;
 
    serv_decode decode
      (
       .clk (clk),
       .i_rst          (i_rst),
-      .i_mtip         (timer_irq),
+      .i_mtip         (i_timer_irq),
+      .i_timer_irq_en (timer_irq_en),
       .i_wb_rdt       (i_ibus_rdt),
       .i_wb_en        (o_ibus_cyc & i_ibus_ack),
       .i_rf_ready     (rf_ready),
@@ -269,7 +269,7 @@ module serv_top
       .i_clk        (clk),
       .i_en         (csr_en),
       .i_cnt        (cnt),
-      .i_mtip       (timer_irq),
+      .i_mtip       (i_timer_irq),
       .o_timer_irq_en ( timer_irq_en),
       .i_csr_sel    (csr_sel),
       .i_csr_source (csr_source),