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https://github.com/olofk/serv.git
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Interrupts working. Adding philosophers example
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@@ -4,6 +4,7 @@ module serv_decode
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input wire clk,
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input wire i_rst,
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input wire i_mtip,
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input wire i_timer_irq_en,
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input wire [31:0] i_wb_rdt,
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input wire i_wb_en,
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input wire i_rf_ready,
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@@ -289,15 +290,11 @@ module serv_decode
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assign o_ctrl_trap = (state == TRAP);
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always @(posedge clk) begin
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if (i_mtip)
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o_csr_mcause[3:0] <= 4'd7;
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else begin
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o_csr_mcause[3:0] <= 4'd0;
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if (i_mem_misalign)
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o_csr_mcause[3:0] <= {2'b01, o_mem_cmd, 1'b0};
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if (e_op)
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o_csr_mcause <= {!op[20],3'b011};
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end
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o_csr_mcause[3:0] <= 4'd0;
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if (i_mem_misalign)
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o_csr_mcause[3:0] <= {2'b01, o_mem_cmd, 1'b0};
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if (e_op)
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o_csr_mcause <= {!op[20],3'b011};
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end
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wire two_stage_op =
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@@ -305,7 +302,15 @@ module serv_decode
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shift_op;
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reg stage_one_done;
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reg mtip_r;
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reg pending_irq;
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always @(posedge clk) begin
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mtip_r <= i_mtip;
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if (i_mtip & !mtip_r & i_timer_irq_en)
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pending_irq <= 1'b1;
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cnt_done <= cnt == 30;
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case (state)
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@@ -314,7 +319,7 @@ module serv_decode
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state <= RUN;
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if (two_stage_op & !stage_one_done)
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state <= INIT;
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if (e_op | i_mtip)
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if (e_op | pending_irq)
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state <= TRAP;
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end
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end
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@@ -331,6 +336,7 @@ module serv_decode
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state <= IDLE;
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end
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TRAP : begin
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pending_irq <= 1'b0;
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if (cnt_done)
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state <= IDLE;
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end
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