github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-02-27 00:39:48 +00:00
Code Issues Releases Wiki Activity

Refactor to separate serv and servant

Browse Source
This commit is contained in:
Olof Kindgren
2019-06-07 10:45:10 +02:00
parent c91a5a43c1
commit cf7e516526
13 changed files with 184 additions and 2204 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
bench/serv_soc_tb.cpp → bench/servant_tb.cpp
View File

@@ -2,7 +2,7 @@
#include <signal.h>
#include "verilated_vcd_c.h"
#include "Vserv_wrapper.h"
#include "Vservant.h"
using namespace std;
@@ -34,7 +34,7 @@ int main(int argc, char **argv, char **env)
char uart_ch = 0;
Verilated::commandArgs(argc, argv);
Vserv_wrapper* top = new Vserv_wrapper;
Vservant* top = new Vservant;
const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
if (arg[0]) {
@@ -55,9 +55,10 @@ int main(int argc, char **argv, char **env)
signal(SIGINT, INThandler);
top->i_clk = 1;
top->wb_clk = 1;
bool q = top->q;
while (!(done || Verilated::gotFinish())) {
top->wb_rst = main_time < 100;
top->eval();
if (tfp)
tfp->dump(main_time);
@@ -96,8 +97,9 @@ int main(int argc, char **argv, char **env)
printf("%lu output q is %s\n", main_time, q ? "ON" : "OFF");
}
}*/
top->i_clk = !top->i_clk;
top->wb_clk = !top->wb_clk;
main_time+=31.25;
}
if (tfp)
tfp->close();

12
bench/serv_top_tb.v → bench/servant_tb.v
View File

@@ -1,18 +1,20 @@
`default_nettype none
module serv_top_tb;
module servant_tb;
parameter memfile = "bitbang.hex";
parameter memfile = "";
reg wb_clk = 1'b1;
reg wb_clk = 1'b0;
reg wb_rst = 1'b1;
reg q_r = 1'b0;
wire q;
always #31 wb_clk <= !wb_clk;
always #31 wb_clk <= !wb_clk;
initial #62 wb_rst <= 1'b0;
vlog_tb_utils vtu();
serv_wrapper #(memfile) dut(wb_clk, q);
servant #(memfile) dut(wb_clk, wb_rst, q);
always @(posedge wb_clk)
if (q != q_r) begin

2048
bitbang.hex
View File

File diff suppressed because it is too large Load Diff

135
serv.core
View File

@@ -21,79 +21,10 @@ filesets:
- rtl/serv_top.v
file_type : verilogSource
ice40_pll:
files:
- rtl/ice40_pll.v : {file_type : verilogSource}
depend : ["fusesoc:utils:generators"]
mem_files:
files:
- sw/blinky.hex : {copyto : blinky.hex}
- sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
file_type : user
serv_top_tb:
files:
- bench/serv_top_tb.v
file_type : verilogSource
depend : [vlog_tb_utils]
wrapper:
files:
- rtl/serv_clock_gen.v
- rtl/riscv_timer.v
- rtl/wb_gpio.v
- bench/serv_arbiter.v
- bench/serv_mux.v
- bench/serv_wrapper.v
file_type : verilogSource
depend : [wb_ram]
netlist:
files: [synth.v : {file_type : verilogSource}]
tinyfpga_bx:
files:
- data/tinyfpga_bx.pcf : {file_type : PCF}
icebreaker:
files:
- data/icebreaker.pcf : {file_type : PCF}
verilator_tb:
files:
- bench/serv_soc_tb.cpp : {file_type : cppSource}
targets:
default:
filesets : [core]
icebreaker:
default_tool : icestorm
filesets : [core, ice40_pll, mem_files, wrapper, icebreaker]
generate: [icebreaker_pll]
parameters : [memfile, memsize, PLL=ICE40_PAD]
tools:
icestorm:
nextpnr_options: [--up5k, --freq, 16]
pnr: next
toplevel : serv_wrapper
synth:
default_tool : icestorm
filesets : [core, mem_files, wrapper, tinyfpga_bx]
toplevel : serv_wrapper
tinyfpga_bx:
default_tool : icestorm
filesets : [core, ice40_pll, mem_files, wrapper, tinyfpga_bx]
generate: [tinyfpga_bx_pll]
parameters : [memfile, memsize, PLL=ICE40_CORE]
tools:
icestorm:
nextpnr_options : [--lp8k, --package, cm81, --freq, 32]
pnr: next
toplevel : serv_wrapper
parameters : [RISCV_FORMAL]
lint:
default_tool : verilator
@@ -103,72 +34,8 @@ targets:
mode : lint-only
toplevel : serv_top
serv_top_tb:
default_tool: icarus
filesets : [core, wrapper, serv_top_tb]
parameters : [RISCV_FORMAL=true, firmware]
toplevel : serv_top_tb
synth_tb:
default_tool: icarus
filesets : [netlist, serv_top_tb]
toplevel : serv_top_tb
verilator_tb:
default_tool: verilator
filesets : [core, wrapper, verilator_tb]
parameters : [RISCV_FORMAL, firmware, memsize, signature, uart_baudrate, vcd]
tools:
verilator:
verilator_options : [--trace]
toplevel : serv_wrapper
parameters:
PLL:
datatype : str
description : PLL type to use for main clock generation
paramtype : vlogparam
RISCV_FORMAL:
datatype : bool
paramtype : vlogdefine
firmware:
datatype : file
description : Preload RAM with a hex file at runtime (overrides memfile)
paramtype : plusarg
memfile:
datatype : file
description : Preload RAM with a hex file at compile-time
paramtype : vlogparam
memsize:
datatype : int
default : 8192
description : Memory size in bytes for RAM (default 8kiB)
paramtype : vlogparam
signature:
datatype : file
paramtype : plusarg
uart_baudrate:
datatype : int
description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
paramtype : plusarg
vcd:
datatype : bool
paramtype : plusarg
generate:
icebreaker_pll:
generator: icepll
parameters:
freq_out : 16
tinyfpga_bx_pll:
generator: icepll
parameters:
freq_in : 16
freq_out : 32

138
servant.core Normal file
View File

@@ -0,0 +1,138 @@
CAPI=2:
name : ::servant:0
filesets:
service:
files:
- servant/ice40_pll.v
- servant/service.v
file_type : verilogSource
depend : ["fusesoc:utils:generators"]
mem_files:
files:
- sw/blinky.hex : {copyto : blinky.hex}
- sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
file_type : user
servant_tb:
files:
- bench/servant_tb.v
file_type : verilogSource
depend : [vlog_tb_utils]
soc:
files:
- servant/servant_clock_gen.v
- servant/servant_timer.v
- servant/servant_gpio.v
- servant/servant_arbiter.v
- servant/servant_mux.v
- servant/servant.v
file_type : verilogSource
depend : [serv, wb_ram]
tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
icebreaker : {files: [data/icebreaker.pcf : {file_type : PCF}]}
verilator_tb: {files: [bench/servant_tb.cpp : {file_type : cppSource}]}
targets:
default:
filesets : [soc]
icebreaker:
default_tool : icestorm
filesets : [mem_files, soc, service, icebreaker]
generate: [icebreaker_pll]
parameters : [memfile, memsize, PLL=ICE40_PAD]
tools:
icestorm:
nextpnr_options: [--up5k, --freq, 16]
pnr: next
toplevel : service
tinyfpga_bx:
default_tool : icestorm
filesets : [mem_files, soc, service, tinyfpga_bx]
generate: [tinyfpga_bx_pll]
parameters : [memfile, memsize, PLL=ICE40_CORE]
tools:
icestorm:
nextpnr_options : [--lp8k, --package, cm81, --freq, 32]
pnr: next
toplevel : service
lint:
default_tool : verilator
filesets : [soc]
tools:
verilator:
mode : lint-only
toplevel : servant
sim:
default_tool: icarus
filesets : [soc, servant_tb]
parameters : [RISCV_FORMAL=true, firmware]
toplevel : servant_tb
verilator_tb:
default_tool: verilator
filesets : [soc, verilator_tb]
parameters : [RISCV_FORMAL, firmware, memsize, signature, uart_baudrate, vcd]
tools:
verilator:
verilator_options : [--trace]
toplevel : servant
parameters:
PLL:
datatype : str
description : PLL type to use for main clock generation
paramtype : vlogparam
RISCV_FORMAL:
datatype : bool
paramtype : vlogdefine
firmware:
datatype : file
description : Preload RAM with a hex file at runtime (overrides memfile)
paramtype : plusarg
memfile:
datatype : file
description : Preload RAM with a hex file at compile-time
paramtype : vlogparam
memsize:
datatype : int
default : 8192
description : Memory size in bytes for RAM (default 8kiB)
paramtype : vlogparam
signature:
datatype : file
paramtype : plusarg
uart_baudrate:
datatype : int
description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
paramtype : plusarg
vcd:
datatype : bool
paramtype : plusarg
generate:
icebreaker_pll:
generator: icepll
parameters:
freq_out : 16
tinyfpga_bx_pll:
generator: icepll
parameters:
freq_in : 16
freq_out : 32

0
rtl/ice40_pll.v → servant/ice40_pll.v
View File

15
bench/serv_wrapper.v → servant/servant.v
View File

@@ -1,21 +1,12 @@
`default_nettype none
module serv_wrapper
module servant
(
input wire i_clk,
input wire wb_clk,
input wire wb_rst,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
serv_clock_gen #(.PLL (PLL))
clock_gen
(.i_clk (i_clk),
.o_clk (wb_clk),
.o_rst (wb_rst));
wire timer_irq;

0
bench/serv_arbiter.v → servant/servant_arbiter.v
View File

2
rtl/serv_clock_gen.v → servant/servant_clock_gen.v
View File

@@ -1,5 +1,5 @@
`default_nettype none
module serv_clock_gen
module servant_clock_gen
(
input wire i_clk,
output wire o_clk,

0
rtl/wb_gpio.v → servant/servant_gpio.v
View File

0
bench/serv_mux.v → servant/servant_mux.v
View File

0
rtl/riscv_timer.v → servant/servant_timer.v
View File

28
servant/service.v Normal file
View File

@@ -0,0 +1,28 @@
`default_nettype none
module service
(
input wire i_clk,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter PLL = "NONE";
wire wb_clk;
wire wb_rst;
servant_clock_gen #(.PLL (PLL))
clock_gen
(.i_clk (i_clk),
.o_clk (wb_clk),
.o_rst (wb_rst));
servant
#(.memfile (memfile),
.memsize (memsize))
servant
(.wb_clk (wb_clk),
.wb_clk (wb_clk),
.q (q));
endmodule