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wip: Add debug instruction counting
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Olof Kindgren
204
rtl/serv_top.v
204
rtl/serv_top.v
@@ -574,6 +574,210 @@ module serv_top
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end
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endgenerate
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reg [4:0] flx_rs1;
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reg [4:0] flx_rs2;
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reg [4:0] flx_imm = 12; //Do we want to check immediate as well?
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reg bit_rs1;
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reg bit_rs2;
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reg [4:0] bit_cnt = 5'd0;
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reg [2:0] funct3;
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reg [4:0] opcode;
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reg [4:0] min_len;
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integer cycles = 0;
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integer saved = 0;
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integer saved_cycles1 = 0;
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integer saved_cycles16 = 0;
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integer saved_cycles_min_12 = 0;
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function automatic [4:0] maxof (input [4:0] a, b);
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begin
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maxof = (a>b) ? a : b;
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end
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endfunction
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function automatic integer maxof3 (input [4:0] a, b, c);
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reg [4:0] tmp;
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begin
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tmp = maxof(a, b);
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maxof3 = {27'd0,maxof(tmp, c)};
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end
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endfunction
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reg LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI,SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND, FENCE, ECALL, EBREAK;
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reg CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI;
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reg OTHER;
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real savings1 = (saved_cycles1*1.0) / (cycles*1.0);
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real savings16 = (saved_cycles16*1.0) / (cycles*1.0);
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real savings_min_12 = (saved_cycles_min_12*1.0) / (cycles*1.0);
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always @(posedge clk) begin
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if (i_ibus_ack) begin
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LUI <= 1'b0;
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AUIPC <= 1'b0;
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JAL <= 1'b0;
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JALR <= 1'b0;
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BEQ <= 1'b0;
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BNE <= 1'b0;
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BLT <= 1'b0;
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BGE <= 1'b0;
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BLTU <= 1'b0;
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BGEU <= 1'b0;
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LB <= 1'b0;
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LH <= 1'b0;
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LW <= 1'b0;
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LBU <= 1'b0;
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LHU <= 1'b0;
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SB <= 1'b0;
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SH <= 1'b0;
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SW <= 1'b0;
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ADDI <= 1'b0;
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SLTI <= 1'b0;
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SLTIU <= 1'b0;
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XORI <= 1'b0;
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ORI <= 1'b0;
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ANDI <= 1'b0;
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SLLI <= 1'b0;
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SRLI <= 1'b0;
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SRAI <= 1'b0;
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ADD <= 1'b0;
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SUB <= 1'b0;
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SLL <= 1'b0;
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SLT <= 1'b0;
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SLTU <= 1'b0;
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XOR <= 1'b0;
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SRL <= 1'b0;
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SRA <= 1'b0;
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OR <= 1'b0;
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AND <= 1'b0;
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FENCE <= 1'b0;
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ECALL <= 1'b0;
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EBREAK <= 1'b0;
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CSRRW <= 1'b0;
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CSRRS <= 1'b0;
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CSRRC <= 1'b0;
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CSRRWI <= 1'b0;
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CSRRSI <= 1'b0;
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CSRRCI <= 1'b0;
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OTHER <= 1'b0;
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casez(i_ibus_rdt)
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// 3322222_22222 11111_111 11
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// 1098765_43210 98765_432 10987_65432_10
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32'b???????_?????_?????_???_?????_01101_11 : LUI <= 1'b1;
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32'b???????_?????_?????_???_?????_00101_11 : AUIPC <= 1'b1;
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32'b???????_?????_?????_???_?????_11011_11 : JAL <= 1'b1;
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32'b???????_?????_?????_000_?????_11001_11 : JALR <= 1'b1;
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32'b???????_?????_?????_000_?????_11000_11 : BEQ <= 1'b1;
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32'b???????_?????_?????_001_?????_11000_11 : BNE <= 1'b1;
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32'b???????_?????_?????_100_?????_11000_11 : BLT <= 1'b1;
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32'b???????_?????_?????_101_?????_11000_11 : BGE <= 1'b1;
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32'b???????_?????_?????_110_?????_11000_11 : BLTU <= 1'b1;
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32'b???????_?????_?????_111_?????_11000_11 : BGEU <= 1'b1;
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32'b???????_?????_?????_000_?????_00000_11 : LB <= 1'b1;
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32'b???????_?????_?????_001_?????_00000_11 : LH <= 1'b1;
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32'b???????_?????_?????_010_?????_00000_11 : LW <= 1'b1;
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32'b???????_?????_?????_100_?????_00000_11 : LBU <= 1'b1;
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32'b???????_?????_?????_101_?????_00000_11 : LHU <= 1'b1;
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32'b???????_?????_?????_000_?????_01000_11 : SB <= 1'b1;
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32'b???????_?????_?????_001_?????_01000_11 : SH <= 1'b1;
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32'b???????_?????_?????_010_?????_01000_11 : SW <= 1'b1;
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32'b???????_?????_?????_000_?????_00100_11 : ADDI <= 1'b1;
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32'b???????_?????_?????_010_?????_00100_11 : SLTI <= 1'b1;
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32'b???????_?????_?????_011_?????_00100_11 : SLTIU <= 1'b1;
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32'b???????_?????_?????_100_?????_00100_11 : XORI <= 1'b1;
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32'b???????_?????_?????_110_?????_00100_11 : ORI <= 1'b1;
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32'b???????_?????_?????_111_?????_00100_11 : ANDI <= 1'b1;
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32'b0000000_?????_?????_001_?????_00100_11 : SLLI <= 1'b1;
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32'b0000000_?????_?????_101_?????_00100_11 : SRLI <= 1'b1;
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32'b0100000_?????_?????_101_?????_00100_11 : SRAI <= 1'b1;
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32'b0000000_?????_?????_000_?????_01100_11 : ADD <= 1'b1;
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32'b0100000_?????_?????_000_?????_01100_11 : SUB <= 1'b1;
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32'b0000000_?????_?????_001_?????_01100_11 : SLL <= 1'b1;
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32'b0000000_?????_?????_010_?????_01100_11 : SLT <= 1'b1;
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32'b0000000_?????_?????_011_?????_01100_11 : SLTU <= 1'b1;
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32'b???????_?????_?????_100_?????_01100_11 : XOR <= 1'b1;
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32'b0000000_?????_?????_101_?????_01100_11 : SRL <= 1'b1;
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32'b0100000_?????_?????_101_?????_01100_11 : SRA <= 1'b1;
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32'b???????_?????_?????_110_?????_01100_11 : OR <= 1'b1;
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32'b???????_?????_?????_111_?????_01100_11 : AND <= 1'b1;
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32'b???????_?????_?????_000_?????_00011_11 : FENCE <= 1'b1;
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32'b0000000_00000_00000_000_00000_11100_11 : ECALL <= 1'b1;
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32'b0000000_00001_00000_000_00000_11100_11 : EBREAK <= 1'b1;
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32'b???????_?????_?????_001_?????_11100_11 : CSRRW <= 1'b1;
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32'b???????_?????_?????_010_?????_11100_11 : CSRRS <= 1'b1;
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32'b???????_?????_?????_011_?????_11100_11 : CSRRC <= 1'b1;
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32'b???????_?????_?????_101_?????_11100_11 : CSRRWI <= 1'b1;
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32'b???????_?????_?????_110_?????_11100_11 : CSRRSI <= 1'b1;
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32'b???????_?????_?????_111_?????_11100_11 : CSRRCI <= 1'b1;
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default : OTHER <= 1'b1;
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endcase
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end
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if (cnt_done & ctrl_pc_en) begin
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if (LUI) saved=0; //LUI and AUIPC Operates on bits 31:12 and
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else if (AUIPC) saved=0; //would need a separate 20-bit MSB detector
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//JAL, JALR, B* : Ignoring branch ops for now, but optimizing especially BNE/BEQ
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//could be very beneficial
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else if (LB) saved = 24; //Can likely optimize data readout. Maybe also
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else if (LH) saved = 16; //speed up address calculation, but not sure
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else if (LW) saved = 0; //
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else if (LBU) saved = 24; //Can likely optimize data readout. Maybe also
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else if (LHU) saved = 16; //speed up address calculation, but not sure
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//SB, SH, SW Not sure how much work to improve SB/SH
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else if (ADDI) saved = 31-maxof3(flx_rs1, 0, flx_imm); // +1 for carry?
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else if (SLTI) saved = 31; //SLT* only needs to write one bit to RD. Rest is
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else if (SLTIU) saved = 31; //zero. Maybe possible to speed up comparison too?
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else if (XORI) saved = 31-maxof3(flx_rs1, 0, flx_imm);
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else if (ORI) saved = 31-maxof3(flx_rs1, 0, flx_imm);
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else if (ANDI) saved = 31-maxof3(flx_rs1, 0, flx_imm);
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//SLLI, SRLI, SRAI: Not sure what can be done here. Probably too much work
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else if (ADD) saved = 31-maxof3(flx_rs1, flx_rs2, 0); // +1 for carry?
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else if (SUB) saved = 31-maxof3(flx_rs1, flx_rs2, 0); // +1 for carry?
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//SLL: Not sure what can be done here. Probably too much work
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else if (SLT) saved = 31; //SLT* only needs to write one bit to RD. Rest is
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else if (SLTU) saved = 31; //zero. Maybe possible to speed up comparison too?
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else if (XOR) saved = 31-maxof3(flx_rs1, flx_rs2, 0);
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//SRL, SRA: Not sure what can be done here. Probably too much work
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else if (OR) saved = 31-maxof3(flx_rs1, flx_rs2, 0);
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else if (AND) saved = 31-maxof3(flx_rs1, flx_rs2, 0);
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else if (FENCE) saved = 32; //This is a nop in SERV
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else if (ECALL) saved = 0; //Not worth optimizing?
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else if (EBREAK) saved = 0; //Not worth optimizing?
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else saved = 0;
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//Minimum 12 cycles
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saved_cycles_min_12 <= saved_cycles_min_12 + ((saved>20) ? 20 : saved);
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//Pretending we have 16-bit granularity
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saved_cycles16 <= saved_cycles16 + ((saved>15) ? 16 : 0);
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saved_cycles1 <= saved_cycles1 + saved;
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end
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cycles <= cycles + 1;
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if (cnt_en) begin
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bit_cnt <= bit_cnt + 5'd1;
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if (cnt0) begin
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bit_rs1 <= rs1;
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bit_rs2 <= rs2;
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flx_rs1 <= 5'd0;
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flx_rs2 <= 5'd0;
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end else begin
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if (rs1 != bit_rs1) begin
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flx_rs1 <= bit_cnt;
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bit_rs1 <= rs1;
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end
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if (rs2 != bit_rs2) begin
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flx_rs2 <= bit_cnt;
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bit_rs2 <= rs2;
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end
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end // else: !if(cnt0)
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end
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end
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`ifdef RISCV_FORMAL
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reg [31:0] pc = RESET_PC;
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