github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-05-03 06:48:37 +00:00
Code Issues Releases Wiki Activity

Reduce warnings

Browse Source
This commit is contained in:
Olof Kindgren
2019-06-24 15:22:08 +02:00
parent 4b371c533f
commit e107627e71
7 changed files with 19 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
rtl/ser_shift.v
View File

@@ -2,7 +2,6 @@
module ser_shift module ser_shift
( (
input wire i_clk, input wire i_clk,
input wire i_rst,
input wire i_load, input wire i_load,
input wire [4:0] i_shamt, input wire [4:0] i_shamt,
input wire i_shamt_msb, input wire i_shamt_msb,

1
rtl/serv_alu.v
View File

@@ -52,7 +52,6 @@ module serv_alu
ser_shift shift ser_shift shift
( (
.i_clk (clk), .i_clk (clk),
.i_rst (i_rst),
.i_load (i_init), .i_load (i_init),
.i_shamt (shamt), .i_shamt (shamt),
.i_shamt_msb (shamt_msb), .i_shamt_msb (shamt_msb),

4
rtl/serv_bufreg.v
View File

@@ -2,8 +2,8 @@ module serv_bufreg
( (
input wire i_clk, input wire i_clk,
input wire i_rst, input wire i_rst,
input wire [4:0] i_cnt, input wire [4:2] i_cnt,
input wire [3:0] i_cnt_r, input wire [1:0] i_cnt_r,
input wire i_en, input wire i_en,
input wire i_clr, input wire i_clr,
input wire i_loop, input wire i_loop,

4
rtl/serv_csr.v
View File

@@ -2,8 +2,8 @@
module serv_csr module serv_csr
( (
input wire i_clk, input wire i_clk,
input wire [4:0] i_cnt, input wire [4:2] i_cnt,
input wire [3:0] i_cnt_r, input wire [3:2] i_cnt_r,
//From mpram //From mpram
input wire i_rf_csr_out, input wire i_rf_csr_out,
//to mpram //to mpram

4
rtl/serv_ctrl.v
View File

@@ -5,8 +5,8 @@ module serv_ctrl
input wire i_rst, input wire i_rst,
input wire i_en, input wire i_en,
input wire i_pc_en, input wire i_pc_en,
input wire [4:0] i_cnt, input wire [4:2] i_cnt,
input wire [3:0] i_cnt_r, input wire [2:1] i_cnt_r,
input wire i_cnt_done, input wire i_cnt_done,
input wire i_jump, input wire i_jump,
input wire i_offset, input wire i_offset,

17
rtl/serv_decode.v
View File

@@ -8,7 +8,7 @@ module serv_decode
input wire [31:0] i_wb_rdt, input wire [31:0] i_wb_rdt,
input wire i_wb_en, input wire i_wb_en,
input wire i_rf_ready, input wire i_rf_ready,
output wire [4:0] o_cnt, output reg [4:0] o_cnt,
output reg [3:0] o_cnt_r, output reg [3:0] o_cnt_r,
output wire o_cnt_done, output wire o_cnt_done,
output reg o_bufreg_hold, output reg o_bufreg_hold,
@@ -75,7 +75,6 @@ module serv_decode
reg [1:0] state; reg [1:0] state;
reg [4:0] cnt;
reg cnt_done; reg cnt_done;
wire cnt_en; wire cnt_en;
@@ -86,8 +85,6 @@ module serv_decode
reg op22; reg op22;
reg op26; reg op26;
assign o_cnt = cnt;
wire running; wire running;
wire mem_op; wire mem_op;
wire shift_op; wire shift_op;
@@ -192,10 +189,10 @@ module serv_decode
end end
assign o_csr_imm = (cnt < 5) ? o_rf_rs1_addr[cnt[2:0]] : 1'b0; assign o_csr_imm = (o_cnt < 5) ? o_rf_rs1_addr[o_cnt[2:0]] : 1'b0;
assign o_csr_d_sel = o_funct3[2]; assign o_csr_d_sel = o_funct3[2];
assign o_alu_shamt_en = (cnt < 5) & (state == INIT); assign o_alu_shamt_en = (o_cnt < 5) & (state == INIT);
assign o_alu_sh_signed = imm30; assign o_alu_sh_signed = imm30;
assign o_alu_sh_right = o_funct3[2]; assign o_alu_sh_right = o_funct3[2];
@@ -203,7 +200,7 @@ module serv_decode
assign o_mem_cmd = opcode[3]; assign o_mem_cmd = opcode[3];
assign o_mem_init = mem_op & (state == INIT); assign o_mem_init = mem_op & (state == INIT);
assign o_mem_bytecnt = cnt[4:3]; assign o_mem_bytecnt = o_cnt[4:3];
assign o_alu_bool_op = o_funct3[1:0]; assign o_alu_bool_op = o_funct3[1:0];
@@ -308,7 +305,7 @@ module serv_decode
if (i_mtip & !mtip_r & i_timer_irq_en) if (i_mtip & !mtip_r & i_timer_irq_en)
pending_irq <= 1'b1; pending_irq <= 1'b1;
cnt_done <= (cnt[4:2] == 3'b111) & o_cnt_r[2]; cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2];
o_bufreg_hold <= 1'b0; o_bufreg_hold <= 1'b0;
@@ -349,13 +346,13 @@ module serv_decode
default : state <= IDLE; default : state <= IDLE;
endcase endcase
cnt <= cnt + {4'd0,cnt_en}; o_cnt <= o_cnt + {4'd0,cnt_en};
if (cnt_en) if (cnt_en)
o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]};
if (i_rst) begin if (i_rst) begin
state <= IDLE; state <= IDLE;
cnt <= 5'd0; o_cnt <= 5'd0;
pending_irq <= 1'b0; pending_irq <= 1'b0;
stage_one_done <= 1'b0; stage_one_done <= 1'b0;
o_ctrl_jump <= 1'b0; o_ctrl_jump <= 1'b0;

12
rtl/serv_top.v
View File

@@ -208,8 +208,8 @@ module serv_top
( (
.i_clk (clk), .i_clk (clk),
.i_rst (i_rst), .i_rst (i_rst),
.i_cnt (cnt), .i_cnt (cnt[4:2]),
.i_cnt_r (cnt_r), .i_cnt_r (cnt_r[1:0]),
.i_en (!(bufreg_hold | o_dbus_cyc)), .i_en (!(bufreg_hold | o_dbus_cyc)),
.i_clr (!mem_en), .i_clr (!mem_en),
.i_loop (bufreg_loop), .i_loop (bufreg_loop),
@@ -229,8 +229,8 @@ module serv_top
.i_rst (i_rst), .i_rst (i_rst),
.i_en (ctrl_en), .i_en (ctrl_en),
.i_pc_en (ctrl_pc_en), .i_pc_en (ctrl_pc_en),
.i_cnt (cnt), .i_cnt (cnt[4:2]),
.i_cnt_r (cnt_r), .i_cnt_r (cnt_r[2:1]),
.i_cnt_done (cnt_done), .i_cnt_done (cnt_done),
.i_jump (jump), .i_jump (jump),
.i_offset (imm), .i_offset (imm),
@@ -350,8 +350,8 @@ module serv_top
serv_csr csr serv_csr csr
( (
.i_clk (clk), .i_clk (clk),
.i_cnt (cnt), .i_cnt (cnt[4:2]),
.i_cnt_r (cnt_r), .i_cnt_r (cnt_r[3:2]),
.i_rf_csr_out (rf_csr_out), .i_rf_csr_out (rf_csr_out),
.o_csr_in (csr_in), .o_csr_in (csr_in),
.i_mtip (i_timer_irq), .i_mtip (i_timer_irq),