Optimize dbus_cyc

rtl/serv_decode.v

@@ -40,6 +40,7 @@ module serv_decode
    output wire 	     o_alu_sh_right,
    input wire 	     i_alu_sh_done,
    output reg [1:0]  o_alu_rd_sel,
+   output wire 	     o_dbus_cyc,
    output wire 	     o_mem_en,
    output wire 	     o_mem_cmd,
    output wire 	     o_mem_init,
@@ -298,6 +299,8 @@ module serv_decode
 
    assign o_rf_rs_en = two_stage_op ? (state == INIT) : o_ctrl_pc_en;
 
+   assign o_dbus_cyc = (state == IDLE) & stage_one_done & mem_op & !i_mem_misalign;
+
    always @(posedge clk) begin
       if (state == INIT)
 	o_ctrl_jump <= take_branch;

rtl/serv_mem_if.v

@@ -17,11 +17,10 @@ module serv_mem_if
    output wire [31:0] o_wb_dat,
    output wire [3:0]  o_wb_sel,
    output wire 	      o_wb_we ,
-   output reg 	      o_wb_cyc,
    input wire [31:0]  i_wb_rdt,
    input wire 	      i_wb_ack);
 
-   wire          wb_en = o_wb_cyc & i_wb_ack;
+   wire          wb_en = i_wb_ack;
 
    reg           signbit = 1'b0;
 
@@ -96,13 +95,5 @@ module serv_mem_if
       if (dat_valid)
         signbit <= dat_cur;
 
-      if (wb_en)
-        o_wb_cyc <= 1'b0;
-      else if (i_init & i_cnt_done & !o_misalign)
-	o_wb_cyc <= 1'b1;
-
-      if (i_rst) begin
-	 o_wb_cyc <= 1'b0;
-      end
    end
 endmodule

rtl/serv_top.v

@@ -168,6 +168,7 @@ module serv_top
       .o_rf_rd_addr   (rd_addr),
       .o_rf_rs1_addr  (rs1_addr),
       .o_rf_rs2_addr  (rs2_addr),
+      .o_dbus_cyc     (o_dbus_cyc),
       .o_mem_en       (mem_en),
       .o_mem_cmd      (mem_cmd),
       .o_mem_init     (mem_init),
@@ -330,7 +331,6 @@ module serv_top
       .o_wb_dat   (o_dbus_dat),
       .o_wb_sel   (o_dbus_sel),
       .o_wb_we    (o_dbus_we ),
-      .o_wb_cyc   (o_dbus_cyc),
       .i_wb_rdt   (i_dbus_rdt),
       .i_wb_ack   (i_dbus_ack));