Add support for DE0 Nano

README.md

@@ -119,6 +119,13 @@ blinky.hex change D10 to H5 (led[4]) in data/arty_a7_35t.xdc).
     cd $SERV/workspace
     fusesoc run --target=arty_a7_35t servant
 
+### DE0 Nano
+
+FPGA Pin D11 (Connector JP1, pin 38) is used for UART output with 57600 baud rate. DE0 Nano needs an external 3.3V UART to connect to this pin
+
+    cd $SERV/workspace
+    fusesoc run --target=de0_nano servant
+
 ### Saanlima Pipistrello (Spartan6 LX45)
 
 Pin A10 (usb_data<1>) is used for UART output with 57600 baud rate (to use

data/de0_nano.sdc

@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

data/de0_nano.tcl

@@ -0,0 +1,11 @@
+set_location_assignment PIN_R8 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+set_location_assignment PIN_A15 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+set_location_assignment PIN_D11 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd
+
+set_location_assignment PIN_J15 -to i_rst_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n

servant.core

@@ -43,6 +43,13 @@ filesets:
       - servant/servclone10_clock_gen.v : {file_type : verilogSource}
       - servant/servclone10.v : {file_type : verilogSource}
 
+  de0_nano:
+    files:
+      - data/de0_nano.sdc : {file_type : SDC}
+      - data/de0_nano.tcl : {file_type : tclSource}
+      - servant/servive_clock_gen.v : {file_type : verilogSource}
+      - servant/servive.v : {file_type : verilogSource}
+
   tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
   icebreaker : {files: [data/icebreaker.pcf  : {file_type : PCF}]}
   alhambra   : {files: [data/alhambra.pcf : {file_type : PCF}]}
@@ -109,6 +116,16 @@ targets:
         device : 10CL025YU256C8G
     toplevel : servclone10
 
+  de0_nano:
+    default_tool : quartus
+    filesets : [mem_files, soc, de0_nano]
+    parameters : [memfile, memsize]
+    tools:
+      quartus:
+        family : Cyclone IV E
+        device : EP4CE22F17C6
+    toplevel: servive
+
   icebreaker:
     default_tool : icestorm
     filesets : [mem_files, soc, service, icebreaker]

servant/servive.v

@@ -0,0 +1,31 @@
+`default_nettype none
+module servive
+(
+ input wire 	   i_clk,
+ input wire 	   i_rst_n,
+ output wire 	   q,
+ output wire 	   uart_txd);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   assign uart_txd = q;
+
+   servive_clock_gen clock_gen
+     (.i_clk (i_clk),
+      .i_rst (!i_rst_n),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule

servant/servive_clock_gen.v

@@ -0,0 +1,34 @@
+`default_nettype none
+module servive_clock_gen
+  (input wire i_clk,
+   input wire i_rst,
+   output wire o_clk,
+   output wire o_rst);
+
+   wire        locked;
+   reg [9:0]   r;
+
+   assign o_rst = r[9];
+
+   always @(posedge o_clk)
+     if (locked)
+       r <= {r[8:0],1'b0};
+     else
+       r <= 10'b1111111111;
+
+   wire [5:0] 	  clk;
+
+   assign 	  o_clk = clk[0];
+
+   altpll
+     #(.operation_mode         ("NORMAL"),
+       .clk0_divide_by         (25),
+       .clk0_multiply_by       (8),
+       .inclk0_input_frequency (20000))
+   pll
+     (.areset       (i_rst),
+      .inclk        ({1'b0, i_clk}),
+      .clk          (clk),
+      .locked       (locked));
+
+endmodule